TIDA-01573: laser recommendation about tida-01573 & lmg1020

Hi Choi,

Thanks for asking about this TIDA. The laser diode we used can not be disclosed with out an NDA in place. The diode itself is 70W in a 3-LCC package from Excelitas. We have also tested using Osram LD as well.

What package do you require? for short pulses of high current, low parasitc inductance from short diode leads is needed.
Check out SPL PL90_3 You can cut the leads to be as short as possible and solder to the board in a low ESL way. If you need higher power you can stack multiple LD. What application is this?

Thanks,

Thank you for your recommendation.

We don't care any package.  Just important thing is higher peak power.  And our application is lidar for automotive.

I want to know laser diode in TIDA.  Plz let me know how to sign NDA bettween  TI and out company.

Have you any ti form for NDA?

Thanks

We are tring to contact with WT MICROELECTRONICS which is TI korean channel .
Can we discuss about NDA with WT MICROELECTRONICS ?

And we bought excelitas sensor through sales channel in korea before .
I think we can buy 100w diode as well. We ordered TPGAD1S09H laser diode already.

I think PCB layout depend on LD. After NDA can you give PCB layout information for us?

thank you.

Thanks for your update Choi,

I think we are on the same page in terms of LD.  Feel free to discuss with WT, is WT doing automotive LiDAR?

can you share your layout so I can help?

Thanks,

pcb lay out.pdfThanks for your reply.

I designed  laser driver once.  But I can't get peak current using my driver with  laser component 's 905d3s3j08x . (pulse width 2ns , Vbus 40V)

I will impove my fault in  my 2nd laser driver.  I am doing PCB artwork this week.

My next design will be similar to TIDA EVM. But i don't know about laser . That's confidential relate to laser  in TIDA01573.

So i try to use  2 laser ( osram: spl pl90_3 and exelitas :  TPGAD1S09H ) you recommended.

But I'm not sure getting higher peak current  even if i improve pcb design and change laser.

Plz let me know any tips  for getting peak current like TIDA-01573. (2ns 50 pk A)

This is my several fault in my 1st design. Before

I attached  pcb lay out.  Circuit is same with TIDA-01573.

1. not split Pgnd , Agnd  , not use kelvin gnd.

2. power loop and Gate loop very long.

SCHEMATIC1 _ LD Driver().pdfHi mueller

r312, 313 is just dummy resister 0 ohm for test.

I argee your recommendation as well.

Let me update pcb design  you recommend.

I dont understand  what via add multiple  mean ? where?

(keep in mind that to reduce inductance with vias add multiple of them)

You mean V bus -> power loop capacitor -> LD's anode pattern is too long?

Or Gnd pattern is too long from c304, c310 's gnd to  lmg1020's gnd .

(I also see the VDD decoupling capacitor's return is not as close as possible as well.)

I have another question. Can i change to 1~2 MLCC which have large capacitance instead of several low capcitor as power loop capacitor.  But same capacitance.

I also attached our circuit.    If i have extra  fault  you can give me any advise.

Thank you.

OSRAM 70W_181015.pdfEXCELITAS 70W_181015.pdf[ 8W VCSEL SERIESX5_181015.pdfVCSEL 40W_181015.pdfhi Jeff

We are desinging 4 laser driver using LMG1020 for higher peak power.

We aready designed artwork. As you recommend I tried to shorten  gate and power loop for reducing inductance  as possible as  I can.

Let me atteched PCB PDF file . If you find any fault  or some need improvement  , plz give me any recommendation.

This is description about our design brifely.  

1. using 4  laser  SPL PL90_3(osram) , TPGAD1S09H(Excelitas),  40W 808nm  CW VCSEL(princeton optronics) , and 8W QCW 850nm VCSEL, (princeton optronics) respectively.

2. 4 layer  and using micro via  for short pattern.

3. dviding GND between power  gnd and gate gnd.  Just only meet kelvin GND in FET.

4. Using same circuit with TIDA-01573 except lasers .

thankyou.

HI Jeff

Thank you for advise. It's very helpful for me.
I reply for your recommendation. But I dont understant all of them.
If you don't mind , could you plz describe more detail

The layout looks a lot tighter.

--> for reducing inductance.

The feed through cap looks really big and can be a 0402 to reduce lead inductance. what cap is your second VDD cap?

-->Our feed through cap is 0603 . that is same size as TI used. I will use YFF15PC0J474MT00(0402) instead of 0603.
Which one is 2nd cap ? C256?
251~254 MLCC are 100v,0.1uF,0603 and 255~256 MLCC are 100v,0.01uF, 0805.

you can also make your traces wider (where ever you see possible) to reduce trace inductance.

-->Which trace I make taces wider ? power trace ? ( power cap->LD -> FET ) or gate trace ?( gate driver -> fet gate)


most important we need to make a plane for the source or GND for the driver so that there is little output impedance from the power loop.
I don't understand what you mean. You mean, I need to make GND and souce of FET pattern wider ?

Fet pin 2(kelvin gnd) is saperated with pin 6,7(source) in layer 2 . Layer2 consist of Power GND and gate Gnd (including kelvin gnd) widely.

check out fig15 from 1020 datasheet. the source connection is made with two vias to the GND plane in the layer below. Then by allowing the plane to span under the part and connecting the IC pin as close as possible with another via creates a giant trace/plane to help with this.

--> I connected between FET's kelvin GND and gate driver gnd using micro via as close as possible . Like EVM board.
Both GND have wide pattern in layer 2.


also try not to cross the input header with the source connection as this might contribute to noise when probing.

--> Input header means J203 (V bus connector) ? not cross I don't understand.

Thanks,

Thanks Choi,

I will be OOO tomorrow and will reply back to you thursday so we can finalize your layout. I can illustrate my ideas better using paint. What my main concern is the distance / trace width of kelvin gnd to driver gnd. It needs to be as short as possible if it is then make it as wide as possible. What are you concerned more about rise time or fall time?  

Thanks,

hi Jeff

I will wait reply for improving pcb artwork before pcb order. My concern is just getting peak power of LD.

I thounght UG, and your advice feed into our design already. I don't know which point I need to renew anymore.

That's why I ask you more detail.

Thank you.