Other Parts Discussed in Thread: ADC12DJ3200EVM, LMK61E2, LMK04828, LMX2594
I am trying to synchronize two ADC12DJ3200EVM boards according to the TIDA-01021 design with TSW1457 data capture boards. I have tested the clocking outputs from the TIDA-01021 board and it appears to be putting out the correct clock and reference signal from the RF out AM1, RF out BM1, RF out AM2 and RF out BM2 outputs. AM1 and AM2 are both putting out ~ 9dBm 2.7 GHz sine wave signals (although not particularly clean) and the BM1 and BM2 outputs are putting out ~ 9dBm 33.75 MHz square wave signals. However, after loading the configure files for TIDA-01021, the TSW14J57 board shows the status D1 ON, D2 OFF, D3 ON, D4 OFF, D5-D8 ON and the HSDC_Pro software gives DDR read to file TIMED_OUT_ERROR.
Here is the startup sequence that I am currently following for synchronizing the boards in detail. The ADC12DJ3200EVM boards have been modified for external clocking as per the ADC12DJ3200EVM documentation, each ADC12DJ3200EVM and TSW14J57 pair has been individually tested and works with a 1 GHz external clock input to both DEVCLK+ and LMK_CLKIN inputs.
1. The 2x ADC12DJ3200EVM and TSW14J57 pairs are connected via a TIDA-01021 board as shown in Figure 1 of TI Designs: TIDA-01021: Multichannel JESD204B 15-GHz Clocking Reference Design for DSO, Radar, and 5G Wireless Testers manual.
2. All 5 boards are powered on
3. Configuration Files for the boards are loaded in this order:
In High Speed Clocking and Data Acquisition GUI
5. 1021_LMX2594_A_B_2.7GCLK_33.75MREF_33.75MPFD_SYSREF_OFF.cfg (for SYSREF OFF, after ADC EVM configuration)
in ADC12DJxx00 GUI
4. Open HSDC Pro GUI and load the ADC12DJxx00_MODE2_trg firmware
At this point the diodes on TSW14J57 read: D1 ON, D2 OFF, D3 ON, D4 OFF, D5-D8 ON
and Capturing data gives: DDR read to file TIMED_OUT_ERROR
1. What is wrong about the start up and synchronization procedure that I am following?
2. Do any of the configuration files or firmware need to be changed to accommodate the TSW1457 boards (the 56 boards are shown in the documentation, not the 57 models that I am using).
3. Are there any additional low level settings that need to be changed to correctly synchronize these boards with this TIDA-01021 design, such as changing the SYSREF frequency on the ADC12DJ3200EVM LMK to 33.75 MHz?
Thanks in advance for your assistance. These questions are very urgent,, we are waiting on testing this synchronization process before we can purchase additional boards ADCEVM and data capture boards.