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TIDA-01629: Analysis of Current Sampling Circuit

Hui Chen
Intellectual 730 points
Part Number: TIDA-01629
Other Parts Discussed in Thread: OPA320, INA240, TIDA-00913, TMS320F28379D, TMS320F28069M

HI!

    In this case, I think there are two problems.Maybe my understanding is incorrect, so I look forward to your help.

    The first one is about the relationship between the bandwidth of control loop, sampling frequency and the bandwidth of  analog circuit in front  of SAR ADC.

     The motor current control loop is generally equal to the switching frequency. Sometimes it can be twice the switching frequency.The switching frequency of Mosfet  is generally less than 100KHz.According to Nyquist's law, in order to prevent frequency aliasing, the bandwidth of the anterior analog circuit of SAR ADC is required to be less than half of the sampling bandwidth of SAR ADC.Despite the high sampling rate of SAR ADC, for the control loop, each control cycle is sampled only once. The control period is equal to the sampling period.  In this circuit board, the bandwidth of current sampling circuit is 500  KHz, which is much larger than that of the current control loop sampling frequency . Is this design unreasonable? Or is my previous statement incorrect?

    The second problem is about the front-stage operational amplifier circuit of SAR ADC.The SAR ADC input circuit requires High bandwidth and Low Slew Rate for operational amplifiers.Operational amplifier INA240 does not seem to meet the requirements.In real applications, do you need to add OPA320 in the back?

Thank you. I look forward to your reply.

 

   

  • 0
    TI__Expert 3300 points
    Hello Tina,

    thank you for your question. You are correct that we need to ensure high frequency noise above half the sampling frequency need to be considered, if present. Now the question is what is more critical for a closed-loop control performance: Noise, current ripple due to PWM or the propagation delay due to a low-pass filter of the phase current sense amplifier.

    Let's assume a 32kHz and a 64kHz current control loop to give an example. As you wrote a current control loop in servo drives is typically equal or twice the PWM rate.

    In that case we execute the current controller and double update the PWM every 16us. The stability of the closed loop current control and the achievable bandwidth (for fast transient torque response) also depends on the phase delay/propagation delay of the overall loop. This includes the propagation delay of the PWM (8us in case of double update), the processor (a C2000 MCU like F28379D can execute FOC including A/D conversion is <1us) and the propagation/phase delay of the phase current measurement.

    Of course we need to be sure the current sampling (typically at the beginning and at the center of the PWM to get the average current) is accurate and noise above the band of interest is less than the accuracy of the signal chain. This noise depends on the individual design. By sampling when no PWM switching occurs we actually avoid switching noise. Another effect by sampling center aligned and at b/o PWM is that we get the average current, of course only if the current ripple is significant. So we avoid our measurement is impacted by a potential current ripple noise which is at the PWM frequency.

    In our design we didn't see significant high frequency noise (after the 2.5us settling time of the INA240 to around 1% accuracy) and we didn't want to limit the bandwidth to introduce additional delay. For example a 20kHz 2nd order low-pass filter would add a phase delay of around 8us.

    If the system has high frequency noise we of course would add an additional low-pass filter, either analog or digital filter along with oversampling. Our C2000 MCU have high-speed ADC and we can e.g. oversample the current signal at 4MSPS and apply post digital filters. In that case we can handle and reject noise up to 2MHz without the need of an additional analog LP filter.

    To your second question:

    The initial design for the R=22 and C2.2nF low-pass filter was the TIDA-00913. It was meant to drive the TMS320F28069M ADC, which has a switched capacitor value of just 1.6pF. The 2.2nF is a factor of more than 1000 larger, so we can charge transfer to more than 10-bit accuracy (0.1%) which is typically good enough. If this is not sufficient we would increase the sample time of the C2000 ADC to allow to settle even better. For the TMS320F28379D ADC which has a 14.5pF switch capacitor, the 2.2nF would not be sufficient and we'd either need to increase the sampling time of the ADC to allow the INA240 drive the F28379D ADC switched capacitor to the required system accuracy of e.g. 0.1%. We'd go here again for the increase sample time w/ the C2000 ADC, but of course if this is not acceptable or desired we may need to add a driver op amp like OPA320.

    If these methods won't work for you and you have or you have more noise, than of course as you wrote you'd need to reduce the passive first order low-pass filter cut-off frequency and even add an additional e.g. 2nd active filter and fast op amp to drive your ADC with the required settling time and accuracy.

    Regards,
    Martin Staebler