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PMP9522: About voltge ratings

Fausto Garcia
Prodigy 90 points
Part Number: PMP9522

Hello 

 I have two questions

 

1.- what is the minimum DC voltage I can switch

2.- where does the maximum voltage to be switched comes from  -- the value (26V) --?

  • 0
    TI__Intellectual 820 points

    Fausto,

    1.- what is the minimum DC voltage I can switch

    Since the back-to-back FETs are turned on/off by a floating gate drive voltage via transformer, there really is no minimum voltage on connectors J1 and J2. The AC or DC input will have a FET voltage drop of Rds_on X Iout, which is quite low and limited by Iout ^2 X Rds_on.

    If you are referring to the minimum voltage for the 12V bias, this is limited to the FETs minimum recommended gate to source voltage of 6V.

    2.- where does the maximum voltage to be switched comes from  -- the value (26V) --?

    26Vac has a peak voltage of 37Vdc. One FET conducts through its body diode while the other must be rated to withstand the applied peak voltage. So each FET must withstand the peak input voltage for an AC input. In this design, 80V max rated FETs were used, so potentially  a higher peak voltage can be applied. However, since there will potentially be significant lead inductance in series with J1/J2, which can cause Vds ringing in the FETs if they are turned off quickly. To alleviate (not totally eliminate) this situation, a bidirectional transorb (D100) rated for 48V was placed across both FETs and a long time constant (1ms) was set for C2/R4 to provide a slow turn-off. The slow turn-off reduces the Vds ring voltage while the transorb begins to clamps voltages above 48V+, but may ring higher based on the current level being switched. So in reality, external parameters play a large role in the maximum applied voltage. For this design, I would limit the maximum input to less than 48Vdc.

  • 0 in reply to John Betten
    Prodigy 90 points

    Hello John

       I was reading another article in ti site about this kind of switches:

    https://e2e.ti.com/blogs_/b/industrial_strength/archive/2016/07/26/a-modern-approach-to-solid-state-relay-design

       But now I have the doubt about how conduction is done, according this article, both MOSFETs conduct through MOSFET itself (not body diode) D-S and S-D, but you mention that one does it through body diode and the other one through the MOSFET itself , could you please clarify?

  • 0 in reply to Fausto Garcia
    TI__Intellectual 820 points

    Fausto,

    Let me clarify. I was referring to when both FETs are in the off state.

    When the SSR circuit is "on", both FETs are on and current does conduct through both MOSFET (not body diodes). When the circuit is off, both FETs have the insufficient gate-source (g-s) voltage to allow current to conduct through the drain-source (d-s) path. But from a voltage withstanding viewpoint, the body diode can drop the d-s voltage of one of the FETs, leaving the other FET to withstand the full input voltage.

    In the PMP9522 example, let's assume V1 is a positive voltage (w.r.t GND) and that there is a load resistor from V2 to GND. When Q1 and Q2 are on, current will flow from V1 to V2 and V2 will see a voltage close to that of V1. When the FETs are turned off, the d-s voltage of Q2 cannot rise above a diode drop, otherwise it will begin to conduct through its body diode. This is what I was referring to in the prior response. This leaves the d-s of Q1 to withstand the full input voltage.

    If V1 is a negative voltage (w.r.t GND), and the FETs are off, the opposite situation happens. The d-s voltage of Q1 must be low (otherwise the body diode conducts), while the d-s voltage of Q2 is left to withstand the full negative voltage. 

    Attached is a TI TINA simulation model that will run for several AC cycles with the FETs on and then turn off. At this point, you can see that each FETsmust withstand 1/2 of the AC cycle only, as mentioned above.

    I hope this helps.SSR1.TSC