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Original question:

TIDA-01629: Analysis of Current Sampling Circuit

TIDA-01629: Analysis of Current Sampling Circuit

Jennifer Stander
Intellectual 470 points
Part Number: TIDA-01629
Other Parts Discussed in Thread: TMS320F28379D, INA240, , TMS320F28388D

Hi,

I think this is probably a noob question, 

We have situation similar to TIDA-01629:  INA240 with the TMS320F28379D (except we are looking at a TMS320F28388D), the 32kHz PWM frequency and 64 kHz current sampling frequency. In your answer to TIDA-01629 it says that you should sample at the beginning and center of the PWM. Sounds good... Then later is says that  "By sampling when no PWM switching occurs we actually avoid switching noise." Our duty cycle can be 0 to 100%. How can you guarantee that you are not sampling when PWM occurs, do you limit your PWM range? Due to other reasons, I can not sample  current too much faster than 64 kHz. If you are sampling during a PWM switching event, what is the best way to get rid of the short glitch at the output of the INA240 caused by the PWM switching? 

Thanks, 

Jennifer

  • 0
    TI__Mastermind 27390 points

    Hi Jennifer,

    That’s a very good question. There needs to be a blanking period before the current can be measured, otherwise the common mode glitch will throw measurements off, even for inline sensors like INA240. I should also add that this glitch is one of most important problems to overcome in order for a current sensing amplifier to be considered inline capable. This is where INA240’s “enhanced PWM rejection” comes in.

    Three phase currents can be sampled; however they are not independent from one another. At any given moment only two are required. While one phase for a moment runs an extreme duty cycle, the other two do not and their information can be used.

    I think the FOC algorithm takes care of the synchronization and calculation automatically.

    Regards, Guang

  • 0 in reply to Guang Zhou
    Intellectual 470 points

    We are not using FOC algorithm and have different constraints. 

    How big does the blanking period need to be?

    Are there any filters at a sweet spot  that would reject the glitches from the switching event and not add significant delay. 

    Thanks,

    Jennifer

  • 0 in reply to Jennifer Stander
    TI__Mastermind 27390 points

    Hi Jennifer,

    A minimum of 2uS, preferably longer wherever possible, should be allowed for the switching disturbances to settle.

    Filtering will not help. The only way to minimize this impact is to stay away from switching edges.

    Regards, Guang