We found layout problem on the TIDA-00195.
In the layout, it places a ground plan which is connected to GND2 for sensitive signal layer on high side IGBT gate driver.
My question is the GND2 for the High side gate driver is coming with high dV/dt. the device and around IC could be influenced by the dV/dt, correct?
On the layout guide of the UCC21732-Q1, it mentions it's only for the low side gate driver, not recommend for high side gate driver.
Hi Brian,
Thanks for the question. In this case, having a ground plane in the same net as switching node will not cause noise issues since the actual high value switching currents do not pass through this plane. This plane mainly acts as the return for the high side gate and other control signal currents. The dv/dt of the switching node also does not affect this plane since the switching node(pins 24. 25 and 26 for phase Y of the IGBT module in this design) is connected to this plane(pin 6 for phase Y of the IGBT module) via a Kelvin connection inside the IGBT module- circled in blue in image below). So the plane you highlight is largely isolated from the high dv/dt effects.
Please let me know if this answers your questions.
Regards
Siva
