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TIDA-00901: Circuit optimization

Part Number: TIDA-00901
Other Parts Discussed in Thread: TIDA-010056, DRV8305, DRV8305-Q1, DRV8350R

Hello,

I am wondering whether it is better to connect C1, C2, and C3 from PVDD to SL_A, SL_B, and SL_C instead of connecting them to ground? Because C1, C2, and C3 are snubber capacitors, they can be better to reduce a surge voltage to protect MOSFETs through connecting them from PVDD (or Drain of high-side MOSFET) to SL (or Source of low-side MOSFET). In TIDA-010056, C10, C11, C12 are connected from VDC to SLx. Could you please comment on this?

Thanks,

John

  • John, hello and good afternoon.  Your E2E question has been forwarded to our Automotive Systems design team.  Please allow us another business day to review and respond to your question  

    Best Regards

    John Fullilove

    Reference Design Operations

    Texas Instruments

  • John,

    I think of C1, C2, and C3 less as snubber capacitors and more as the fast bulk capacitors, in conjunction with C8 and C9.  You are right that in many designs snubber capacitors are used, often to reduce the "ringing" overshoot during PWM transitions.  But we have found that by using the adjustable "smart drive" (IDRIVE and TDRIVE) settings of the DRV8305, snubbers are not needed.  

    If you refer to the DRV8305-Q1 EVM, you can see Q3 and Q6 are provided across the FETs, but are not populated (DNP note).

    If you prefer to include snubbers across the FETs of each phase, then connecting them as you describe would be appropriate.

  • Hi Clark,

    Thanks for your reply. However, I am still puzzled with the pros and cons of connecting these capacitors to SLx vs. to ground. In TIDA-010056, C10, C11, C12 are connected from VDC to SLx and DRV8350R used in TIDA-010056 is a smart gate driver as well.

    Thanks and I look forward to hearing from you,

    John

  • John,

    In TIDA-010056 the decoupling capacitors C10, C11 and C12 will allow a low-impedance path for high-frequencies, such as during sharp transitions, across the high-side and low-side FETs.  These are discussed in section 2.4.1 of the TIDA-010056 design guide. Note that SLx is connected to GND by R24 and R25 in parallel, a combination of 0.5 milliohms.