Other Parts Discussed in Thread: TPS3808, TPS2372, TPS2373
I have a few questions regarding this design:
- Why is there a need for the UVLO of the converter to be pulled low by Q9? I thought that unless the inrush phase is finished, PG stays low and disconnects PWR_GND from RTN1. Shouldn’t the converter be off even without pulling UVLO low?
- What is the reason for having Q5, Q9, Q10, and Q12? Can one not go straight to Q9?
- I assume that D9 and D10 are used for protection. What situation would potentially cause them to conduct? Perhaps when Q11 turns on and there is a difference in voltage between DC and POE?
- What are D14 and D16 for? For D16 case, isn't Q11 already blocking current flow during classification?
- What is the TPS3808 used for?