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WEBENCH® Tools/TPSM82822: I want to simulate the transfer function of TPSM82822.

yuichi shintomi
Intellectual 315 points
Part Number: TPSM82822

Tool/software: WEBENCH® Design Tools

Hello team,

I use TPSM82822 for FPGA I/O power supply.
There are two types, 1.8V/1.5Amax and 1.03V/1.5Amax.
Other FPGA power supplies are also designed with TI's TPSM.
For other FPGA power supplies, the transfer function could be simulated with WEBENCH® Designer, but TPSM82822 is a new product, so it is not supported.
I hope that my TPSM82822 design (attached material) will be simulated for the transfer function.
Can you please?
Thank you and best regards,
Yuichi Shintomi
  • 0
    TI__Intellectual 1490 points

    Hi Yuichi Shontomi,

    When you say "Transfer Function" - I am assuming you are talking about AC simulation to view loopGain bode plots. This device operates in DCS control architecture - which is a non-linear control scheme. We generally do not have AC spice models or Transfer function equations for devices which operate in DCS, DCAP control modes.

    We have the PSPICE transient model available in the product folder and you can do transient simulations to verify the design. We have a plan to also integrate the transient simulations into WEBENCH - but this will take time and expect to be available after the product is released (currently in preview).

    If you need further design help for this device, we can move the post to the right forum so the respective product support team can help. Also I see that your attachments did not get through - can you please re-attach the material you are trying to share.

    Regards,

    Srikanth Pam 

    Online Design Tools

  • 0 in reply to Srikanth Pam
    Intellectual 315 points

    Hi Srikanth Pam,

    Thanks for the info.I also try Pspice.If possible, I'd be happy if the product support team could confirm the design.

    Try attaching the material again.
    Thank you and best regards,
    Yuichi Shintomi

    20200803_TPSM82822_1.8V_Design.pdf

    20200803_TPSM82822_1.03V_Design.pdf

  • 0 in reply to yuichi shintomi
    TI__Intellectual 1490 points

    Hi Yuichi Shontomi,

    Thank you for attaching the designs -  I looped in product support team to review the design. You will hear from the team shortly. Thank you for your patience.

    Regards,

    Srikanth Pam

    Online Design Tools

  • 0 in reply to Srikanth Pam
    TI__Guru*** 142860 points

    Hi Shintomi-san,

    Thank you for using the new TPSM82822 and our Webench tool.

    It seems like you have manually modified the design from what Webench generated.  This is perfectly acceptable to use your preferred suppliers, etc.

    Both of your designs do contain less than the minimum required 5 uF effective Cout.  The output capacitance needs to be increased.

    Do you have additional capacitance at the input to the FPGA?  Usually, an FPGA requires higher values of capacitance instead of lower ones.

  • 0 in reply to Chris Glaser
    Intellectual 315 points

    Hi Chris-San

    Thank you for contacting.

    Please talk about the point of increasing the output capacitor.
    1. I will add MLCC 0.1uF.
    2..Add decoupling capacitors to the power supply path to the FPGA using the Power Delivary Network Tool.
    3.I plan to use 2pcs of GRM188R61E475KE11D. Should I use 3pcs? (I am concerned about the phase margin.)
    I'm trying to design it like this. Please give us your opinion.
    Thank you and best regards,
    Yuichi Shintomi
  • 0 in reply to yuichi shintomi
    TI__Guru*** 142860 points

    Hi Shintomi-san,

    Please follow the D/S requirement to have at least 5 uF effective Cout on the output.  This includes all capacitors on the output.

    For best phase margin, keep the total capacitance below 47uF effective.