This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TIDA-00120: Considerations when increasing output charging current to 40A

Part Number: TIDA-00120
Other Parts Discussed in Thread: CSD18532KCS, CSD18502KCS, UCC27211, CSD18502Q5B, CSD18532Q5B, CSD18540Q5B, CSD18531Q5A

I am trying to implement a slightly different version of the TIDA-0120 charge controller that will support up to 40A charging current and I have some questions I hope someone can help me with.

  1. What actually defines the max charging current? Is there a current limiting mechanism in the MSP430 FW that defines the max charging current?
  2. You have a hint in the board description that although the design is for 20A, up to 40A could be possible by choosing a different MOSFET package. I thus intend to use CSD18532KCS and CSD18502KCS in TO-220 case, but with heatsinks. Do you find this a good enough choice?
  3. Apart from the MOSFETs I also have some concerns regarding the two 10uH inductors, L1 and L2. If I understand the circuit correctly, these should also be exposed to the full extent of the charging current. I guess I have to change the inductors as well, and choose some that can go up to 40A? Problem is of course that I cannot find 10uH / 40A inductors. Perhaps I could decrease the inductance and then increase the capacitance of the filter (C3, C9, C8)?
  4. What about R2 (and R1 potentially)? Don't I have to find another sense resistor that doesn't overheat with 40A? If I'm not mistaken, the existing one is right at the border.
  5. Any other component I should consider with the increased current?

  • Hi Nikos,

    The maximum charging current is a limitation imposed by the hardware. We need to change the MOSFETs and the inductor (the current sense as well) to increase charging current.

    I think your choice of devices is correct for the current.

    You need to choose inductors with 20A+ rating, as the current is split between two phases. Even with imbalance, there is no need to go for more than 30A rating. As the current is higher, the inductance value is going to come down. Please use standard buck converter equations to re-calculate values.

    Yes, the current sense resistors also need to change to a lower value, higher current one. It is preferable to use a separate current shunt amplifier at this high current to avoid noise pick-up.

    The gate driver also need to be changed. You can go for a dual driver like UCC27211.



  • Hi Nikos,

    Thanks for the inquiry. I am the applications support for TI's power MOSFETs. I was not involved in this design but will try to help you out. What is the input voltage range for your design? Does it need to support the same 15Vin to 44Vin as the reference design? This is a two phase, synchronous buck charger and each phase carries half of the output current or 20A in your application. You need to select an inductor to carry 20A DC current plus ripple current. The CSD18532Q5B is used for the high side and low side FETs of the sync buck. The CSD18502Q5B is used for the input and output cutoff switches. Q1 carries the input current andQ6/ Q7 the output current. For the sync buck FETs, I am including a link to TI's synchronous buck FET selection tool below. This tool allows you to compare up to 3 different FET solutions for your design.

    In order to double the output current of the charger, you may need to select FETs with lower on resistance and/or alternative packages. The reference design uses devices in a 5x6mm SON package which can dissipate a maximum of ~3W with a good multilayer PCB design. TI does have alternative packages such as D2PAK (SMT) and TO220 (thru-hole, heat sinkable) that can dissipate more power. Depending on the input voltage, you might have to parallel FETs to dissipate the heat. Right now, the tool does not accommodate parallel FETs (will add in future revision).

    To answer your questions:

    1. I have an email into the design team to see how the current limit is set for this reference design.
    2. Please try the FET selector tool in the link below. Also, I need to know the input voltage range.
    3. There are many design variables. For example, you can increase the switching frequency to decrease the output inductor value. Since I am not familiar with this design, I have referred this to the design team.
    4. You may have to parallel current sense resistors. Referred to design team.
    5. Any component, connector or cable in the charging path should be sized for the higher output current.

    I look forward to your response.

  • Hi Salil,

    thank you for your answer.

    Without wanting to go against you, it is difficult for me to believe that the current is limited by the hardware. I mean, of course if the components (MOSFETs, inductors etc.) cannot support x amount of Amperes, you simply cannot have this charging current. But on the other hand there must be a mechanism in the FW that limits the current used for charging.

    Thanks for the suggestions re: the inductor rating. It appears I don't know the theory well. Could you point me to some article I could consult for the equations and the theory behind them?

    Do you mind elaborating a bit on why you suggest that the existing current sensing solution will lead to high noise pick-up?

    I'm also curious to understand why you say I need to change the gate driver. I see that the new driver you are proposing can source higher driving current. Is that the reason? If yes, why we need this?


  • Hi John,

    really appreciate the time you spent to reply to my post.

    To answer your question re: the input voltage, my target is to be able to only charge 24Vout batteries, from PV cells at 44Vin.

    It seems that unfortunately I am missing some theoretical background about this 2-phase buck converter topology. Any chance you could send me some references where I can read on the subject?

    Thanks also for the MOSFET selection tool, I will try to have a look. Although from a first glance I think there are some input fields that I'm not quite sure what to fill in.

    I didn't get what you meant that depending on the input voltage, I may need to parallel multiple MOSFETs to improve heat dissipation. Doesn't that only depend on the current?

    Best regards,

  • Hi Nikos,

    TI has training materials available at the link below. You may be particularly interested in the topics in the links following it. A 2-phase buck converter is simply two sync buck converter power stages in parallel switching 180 degrees out of phase. MOSFET conduction losses are proportional to current squared whereas switching losses a dependent on voltage, current, switching frequency and switching speed of the MOSFET. Switching losses increase with input voltage.

  • Hi Nikos,

    Following up to see if we have resolved your issue. Please let us know if you have any additional questions.

  • Hi John,

    I still need to study the training materials you recommended.
    Apart from that, I thought you were waiting some answers from the design team? Or is my impression wrong?

    Best regards,

  • Hi Nikos,

    Thanks again for your interest in TI FETs. After reviewing your requirements, I would recommend using 2 x high side and 2 x low side FETs in parallel in each phase of the sync buck charger. You can always remove one parallel FET if it is not needed. Furthermore, I would use the 5x6 SON packaged FETs instead of TO-220 packaged devices. This is because the TO-220 has much higher parasitic inductance due to the thru-hole leads and internal wire bonds on the source connection to the die and will not perform well at higher switching frequency because of higher switching losses. As a starting point, I would recommend 2x CSD18531Q5A for the low side FETs and  2x CSD18540Q5B for the high side FETs. When paralleling FETs, make sure to use a small value gate resistor for each FET.