PMP22557: Change the design to 5V output

Hello John,

Many thanks for the detail guidelines and explanation.

I would like to confirm one more question , since the case is battery supply so the standby power loss would be very sensitive，so what is the standby power loss? Also is it possible to provide SPICE model to do the simulation for the new change ?

Thank you very much

Rick

Got it ,Thanks John

Hi John,

I still don't very clear about taking Vin as reference. At startup, the controller is supplied from HV(Vin), but the GND pin4 is not connected with reference GND of Vin(NMOS is turned off at startup ), so there is no return path, how does controller work, can you explain it more, I have never see such trick design before

Many thanks to you

Hi Rick,

Information on the operation of the controller is within the UCC28730 datasheet. Paragraph 7.3.7/8 and detail the controller's startup behavior. There are many modes or states of operation for this device. In this particular application, where GND is floated on the switchnode and the FET is off initially, the return path from Vin to GND is as follows: Vin to HV which sources a current into the VDD cap to charge it. VS is initially internally shorted to the GND pin. Return current is then through R1 (top resistor of divider), R8/R9, into Cout back to input GND. If Cout is charged up some, this can shift the converter's start voltage higher by the amount of voltage it is charged to. In this application, the voltage across R1 (and R8/R9) is monitored to determine the startup voltage. Once the controller is running and the converter is in regulation, the current source drops from 225uA to 80uA which lower the controller's turn off voltage. The controller starts up in a CC mode detailed below.

Hope this helps.

7.3.7 Startup Operation
An internal high-voltage startup switch, connected to the bulk capacitor voltage (VBULK) through the HV pin,
charges the VDD capacitor. This startup switch functions similarly to a current source providing typically 250 μA
to charge the VDD capacitor. When VVDD reaches the 21-V UVLO turn-on threshold, the controller is enabled, the
converter starts switching, and the startup switch turns off.
At initial turn-on, the output capacitor is often in a fully-discharged state. The first 4 switching-cycle current peaks
are limited to IPP(min) to monitor for any initial input or output faults with limited power delivery. After these 4
cycles, if the sampled voltage at VS is less than 1.32 V, the controller operates in a special startup mode. In this
mode, the primary-current-peak amplitude of each switching cycle is limited to approximately 0.67 x IPP(max) and
DMAGCC increases from 0.432 to 0.650. These modifications to IPP(max) and DMAGCC during startup allow highfrequency
charge-up of the output capacitor to avoid audible noise while the demagnetization voltage is low.
Once the sampled VS voltage exceeds 1.36 V, DMAGCC is restored to 0.432 and the primary-current peak
resumes as IPP(max). While the output capacitor charges, the converter operates in CC mode to maintain a
constant output current until the output voltage enters regulation. Thereafter, the controller responds to conditions
as dictated by the control law. The time to reach output regulation consists of the time the VDD capacitor
charges to VVDD(on) plus the time the output capacitor charges.

7.3.8 Fault Protection
The UCC28730 provides comprehensive fault protection. The protection functions include:
1. Output Overvoltage
2. Input Undervoltage
3. Internal Overtemperature
4. Primary Overcurrent fault
5. CS-pin Fault
6. VS-pin Fault
A UVLO reset and restart sequence applies to all fault-protection events.
The output-overvoltage function is determined by the voltage feedback on the VS pin. If the voltage sample of VS
exceeds 4.6 V for three consecutive switching cycles, the device stops switching and the internal current
consumption becomes IFAULT which discharges the VDD capacitor to the UVLO-turn-off threshold. After that, the
device returns to the start state and a start-up sequence ensues.
Current into the VS pin during the MOSFET on time determines the line-input run and stop voltages. While the
VS pin clamps close to GND during the MOSFET on time, the current through RS1 is monitored to determine a
sample of VBULK. A wide separation of the run and stop thresholds allows clean start-up and shut-down of the
power supply with line voltage. The run-current threshold is 225 μA and the Stop-current threshold is 80 μA. The
input AC voltage to run at start-up always corresponds to the peak voltage of the rectified line, because there is
no loading on CBULK before start-up. The AC input voltage to stop varies with load since the minimum VBULK
depends on the loading and the value of CBULK. At maximum load, the stop voltage is close to the run voltage,
but at no-load condition the stop voltage can be approximately 1/3 of the run voltage.
The UCC28730 always operates with cycle-by-cycle primary-peak current control. The normal operating range of
the CS pin is 0.74 to 0.249 V. An additional protection occurs if the CS pin reaches 1.5 V after the leading-edge
blanking interval for three consecutive cycles, which results in a UVLO reset and restart sequence.
Normally at initial start-up, the peak level of the primary current of the first four power cycles is limited to the
minimum VCST(min). If the CS input is shorted or held low such that the VCST(min) level is not reached within 4 μs on
the first cycle, the CS input is presumed to be shorted to GND and the fault protection function results in a UVLO
reset and restart sequence. Similarly, if the CS input is open, the internal voltage is pulled up to 1.5 V for three
consecutive switching cycles and the fault protection function results in a UVLO reset and restart sequence.
The internal overtemperature-protection threshold is 165°C. If the junction temperature reaches this threshold,
the device initiates a UVLO-reset cycle. If the temperature is still high at the end of the UVLO cycle, the
protection cycle repeats.
Protection is included in the event of component failures on the VS pin. If complete loss of feedback information
on the VS pin occurs, the controller stops switching and restarts.