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PMP22557: Change the design to 5V output

Part Number: PMP22557
Other Parts Discussed in Thread: UCC28730

My design input voltage is range from 70V~120V, and the output expected to be 5V, load is about 50mA, applied for automotive

1.   Is it  ok to bear from 70~120V input for PMP22557

2. Is it ok to change the PMP22557 to 5V output ? how to change

3. I see UCC28730 is for a flyback controller , but it looks like the PMP22557 is not designed as a flyback, is that ok?

  • Hi Rick,

    I can give you suggested component changes to modify PMP22557 for your application.

    My design input voltage is range from 70V~120V, and the output expected to be 5V, load is about 50mA, applied for automotive

    1.   Is it  ok to bear from 70~120V input for PMP22557

    Yes, this design "floats" the UCC28730 controller on the switch node and can easily tolerate 120Vdc in this application.

    2. Is it ok to change the PMP22557 to 5V output ? how to change

    The controller must operate in DCM only. To change the design for your specs, I recommend the following changes to PMP22557:

    1) L1 > 120uH, so I recommend using 150uH. The inductor value must increase because your output power is much less. The expected Ipeak = 0.3A and Irms = 0.1A, so chose an appropriate rated inductor.

    2) R6 < 3.2 ohms to prevent hitting OC, so I recommend using 2.5 ohms max. Irms ~ 26mA, so an 0603 or 0805 is adequate.

    3) Q1 is ok and will work but is overkill for this low output power. Conduction and switching losses should be quite low. If you change FETs, a FET with 1 ohm Rdson should not be a problem. Select a FET with very low gate charge (10nC or less) and rated for >Vin max.

    4) C4 should be >50uF and have an ESR<0.1 ohm. A 100uF alum (low ESR) should be fine.

    5) C1 = 10uF min is recommended. I recommend keeping the 25V rating to account for cap reduction due to DC bias.

    6) R1 = 200k (this also sets the start voltage)

    7) R2 = 845k

    8) R8 + R9 ~ 30K. You can use one resistor here, not two Their total value also sets the converter's turn on/off levels.

    9) R7 = 7.50k. This is a preload to prevent Vout from increasing when under no load.

    10) R5 ~ 4.2k.

    3. I see UCC28730 is for a flyback controller , but it looks like the PMP22557 is not designed as a flyback, is that ok?

    Since the controller's GND pin is on the switch node, all control signals are referenced to either Vin or GND (actually -0.7V). The HV pin can easily tolerate your input voltage for startup. But once running, the internal HV FET turns off and bias power is taken from the output voltage through D1 + D2 to charge C1 (when Q1 is off, D3 conducts). Regulation is maintained (sensed) through D2/R1/R2. D2 forward drop will mostly cancel with the D3 forward drop. VS senses the output and controls the PWM. The VS pin is very sensitive and should NOT be probed because it will effect regulation. It is recommended that a PCB layout similar to the one used for PMP22557 be used. 

    Best regards,

    John Betten

  • Hello John,

    Many thanks for the detail guidelines and explanation.

    I would like to confirm one more question , since the case is battery supply so the standby power loss would be very sensitive,so what is the standby power loss? Also is it possible to provide SPICE model to do the simulation for the new change ?

    Thank you very much


  • Hi Rick,

    Based on the PMP22557 design, no-load input power and input current was measured as the following (Vout = 12.2V):

    Pin =23mW, Iin = 381uA, (Vin = 60Vdc)

    Pin =29mW, Iin = 319uA, (Vin = 90Vdc)

    Pin =37mW, Iin = 304uA, (Vin = 120Vdc)

    Keep in mind that the converter is operating and the output is regulated to 12.2V. There is a 10K 'preload" resistor on the output which dissipates ~15mW alone, so the actual converter power requirement is about 1/2 of the above. However, the preload limits the output voltage rise with no-load and the actual value should be determined during testing.

    I do not have a PSPICE model for this circuit, but you can download "PSPICE for TI" from the link below for free. There is a transient model of the UCC28730 controller in the library.


    John Betten

  • Got it ,Thanks John

  • Hi John,

    I still don't very clear about taking Vin as reference. At startup, the controller is supplied from HV(Vin), but the GND pin4 is not connected with reference GND of Vin(NMOS is turned off at startup ), so there is no return path, how does controller work, can you explain it more, I have never see such trick design before

    Many thanks to you

  • Hi Rick,

    Information on the operation of the controller is within the UCC28730 datasheet. Paragraph 7.3.7/8 and detail the controller's startup behavior. There are many modes or states of operation for this device. In this particular application, where GND is floated on the switchnode and the FET is off initially, the return path from Vin to GND is as follows: Vin to HV which sources a current into the VDD cap to charge it. VS is initially internally shorted to the GND pin. Return current is then through R1 (top resistor of divider), R8/R9, into Cout back to input GND. If Cout is charged up some, this can shift the converter's start voltage higher by the amount of voltage it is charged to. In this application, the voltage across R1 (and R8/R9) is monitored to determine the startup voltage. Once the controller is running and the converter is in regulation, the current source drops from 225uA to 80uA which lower the controller's turn off voltage. The controller starts up in a CC mode detailed below.

    Hope this helps.

    7.3.7 Startup Operation
    An internal high-voltage startup switch, connected to the bulk capacitor voltage (VBULK) through the HV pin,
    charges the VDD capacitor. This startup switch functions similarly to a current source providing typically 250 μA
    to charge the VDD capacitor. When VVDD reaches the 21-V UVLO turn-on threshold, the controller is enabled, the
    converter starts switching, and the startup switch turns off.
    At initial turn-on, the output capacitor is often in a fully-discharged state. The first 4 switching-cycle current peaks
    are limited to IPP(min) to monitor for any initial input or output faults with limited power delivery. After these 4
    cycles, if the sampled voltage at VS is less than 1.32 V, the controller operates in a special startup mode. In this
    mode, the primary-current-peak amplitude of each switching cycle is limited to approximately 0.67 x IPP(max) and
    DMAGCC increases from 0.432 to 0.650. These modifications to IPP(max) and DMAGCC during startup allow highfrequency
    charge-up of the output capacitor to avoid audible noise while the demagnetization voltage is low.
    Once the sampled VS voltage exceeds 1.36 V, DMAGCC is restored to 0.432 and the primary-current peak
    resumes as IPP(max). While the output capacitor charges, the converter operates in CC mode to maintain a
    constant output current until the output voltage enters regulation. Thereafter, the controller responds to conditions
    as dictated by the control law. The time to reach output regulation consists of the time the VDD capacitor
    charges to VVDD(on) plus the time the output capacitor charges.

    7.3.8 Fault Protection
    The UCC28730 provides comprehensive fault protection. The protection functions include:
    1. Output Overvoltage
    2. Input Undervoltage
    3. Internal Overtemperature
    4. Primary Overcurrent fault
    5. CS-pin Fault
    6. VS-pin Fault
    A UVLO reset and restart sequence applies to all fault-protection events.
    The output-overvoltage function is determined by the voltage feedback on the VS pin. If the voltage sample of VS
    exceeds 4.6 V for three consecutive switching cycles, the device stops switching and the internal current
    consumption becomes IFAULT which discharges the VDD capacitor to the UVLO-turn-off threshold. After that, the
    device returns to the start state and a start-up sequence ensues.
    Current into the VS pin during the MOSFET on time determines the line-input run and stop voltages. While the
    VS pin clamps close to GND during the MOSFET on time, the current through RS1 is monitored to determine a
    sample of VBULK. A wide separation of the run and stop thresholds allows clean start-up and shut-down of the
    power supply with line voltage. The run-current threshold is 225 μA and the Stop-current threshold is 80 μA. The
    input AC voltage to run at start-up always corresponds to the peak voltage of the rectified line, because there is
    no loading on CBULK before start-up. The AC input voltage to stop varies with load since the minimum VBULK
    depends on the loading and the value of CBULK. At maximum load, the stop voltage is close to the run voltage,
    but at no-load condition the stop voltage can be approximately 1/3 of the run voltage.
    The UCC28730 always operates with cycle-by-cycle primary-peak current control. The normal operating range of
    the CS pin is 0.74 to 0.249 V. An additional protection occurs if the CS pin reaches 1.5 V after the leading-edge
    blanking interval for three consecutive cycles, which results in a UVLO reset and restart sequence.
    Normally at initial start-up, the peak level of the primary current of the first four power cycles is limited to the
    minimum VCST(min). If the CS input is shorted or held low such that the VCST(min) level is not reached within 4 μs on
    the first cycle, the CS input is presumed to be shorted to GND and the fault protection function results in a UVLO
    reset and restart sequence. Similarly, if the CS input is open, the internal voltage is pulled up to 1.5 V for three
    consecutive switching cycles and the fault protection function results in a UVLO reset and restart sequence.
    The internal overtemperature-protection threshold is 165°C. If the junction temperature reaches this threshold,
    the device initiates a UVLO-reset cycle. If the temperature is still high at the end of the UVLO cycle, the
    protection cycle repeats.
    Protection is included in the event of component failures on the VS pin. If complete loss of feedback information
    on the VS pin occurs, the controller stops switching and restarts.