TIDA-00366: what is the benefit of connecting both side power to each other?

Dear Dave, 

The IGBT module is designed for collector currents of 85A, or based on VCE(max) of ~2.4V and max power of 290W the total of all threee could be around 120 A. This is quite a lot for the module power pins so we need multiple connections in parallel, regardless how strong they are internally connected. In this design all 4 pins are connected to the pcb with shortest possible trace inbetween (running in parallel to the assumed on module path). That should minimize any loop effects so they won't occure in the low frequency range the module is operated. During the rise time of the IGBT the signal could travel more than 8 meters and the 7.5 cm on the module/pcb are relatively short compared to that. 

Please let me know whether this answers the question. 

Best regards, Ingolf

Hi Dave, you had an other set of questions open which I missed. Sorry for that. Unfortunately the thead is closed. If you still need them answered you may send me pn to my first name dot last name at ti.com. To recap these were regarding TIDA-00195 and I'll answer them here as a replacement:

question 1:if I use a parallel 10nf cap  along with GE(gate input cap =10nf) it will draw current 2 times more?

answer: the gate driver will draw a bit more current. How significant this is needs to be simulated but I think the effect will be neglible. The primary goal is to control slew rates and to prevent self turn on of the IGBT. Different power modules have different input capacitance so you can use the cap to trim the behavior towards your needs.

Question 2: as you said

• reduce the relative effect from the Miller capacitance :do you mean it will help to shorten the rising time(on time)? 

answer: it will make the rise time longer so the percentage of influence of the Miller cap is reduced. Also it reduces the tendency of self turn on if an if the other transistor in the half bridge turns on. The description is in chapter 6.4.9 of the user guide of TIDA-00195.

question 3:
   sorry I could not get your point !

• on purpose reduce the the rising and falling time to what is needed to pass EMI regulations : what do you mean?

       as far as I know Having two cap in parallel, make charging time and discharging time to be doubled . and it drawing current is also  become doubled.

          which both of them are harmful for switching .please correct me if I am wrong...

          how this parallel cap can reduce the the rising and falling time  ?

answer: I meant to say "slow down the switching speed" i.e. increase the rise and fall time. At low switching speed a fast rise and fall is not so much needed and the EMI of those unwanted. So making them slower reduses EMI dramatically at the expense of a bit of efficiency.

question 4: 

• stabilize the propagation delay and make it independent from load :you mean by drawing current rising time and falling time will increase but if we put the parallel cap can stabilize the propagation delay  ? is that what you mean?

answer: I meant to balance the turn on and turn off speed and minimize or eliminate simultaneous on time of both parts of the half bridge. The cap can help to tune this. Since the design is an evaluation platform the designer intended giving as much control of the switching process as possible.