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LMR50410-Q1: SIMetrix Error-Unknown parameter for LMR50410-Q1

Thamizhmaran Elangovan — Fri, 05 Jun 2026 07:33:50 GMT

Part Number: LMR50410-Q1

Hi,

I am currently working with the LMR50410-Q1 buck regulator and downloaded the Spice model directly from the Texas Instruments website (SLUM747.ZIP).

I have imported and installed this model into the SIMetrix simulator environment.

However, when attempting to run the transient simulation, the simulator aborts and throws the following parameter expression error,.

*** ERROR *** Error in parameter expression 'vout/i_trans' (Line ref: design.net,484)
Unknown parameter 'vout'

Could you please assist with the following?

Is there a specific global parameter or variable definition (like .param vout = ?) that needs to be manually added to the simulation schematic for this model.?

I have attached screenshots of the specific model downloaded and the error log for your reference.

LM5146DESIGN-CALC: TI website LM5146-Q spice model Error

Milind Madane — Fri, 05 Jun 2026 05:54:28 GMT

Part Number: LM5146DESIGN-CALC
Other Parts Discussed in Thread: LM5146, LM5146-Q1, LM5146-Q1-EVM12V

Hello Team ,

I am currently working on an LTspice simulation of a DC-DC converter, and we are using the LM5146 SPICE model in LTspice simualtion. However, we are facing an issue with the model

*$
* LM5146-Q1
*****************************************************************************
* (C) Copyright 2018 Texas Instruments Incorporated. All rights reserved.
*****************************************************************************
** This model is designed as an aid for customers of Texas Instruments.
** TI and its licensors and suppliers make no warranties, either expressed
** or implied, with respect to this model, including the warranties of
** merchantability or fitness for a particular purpose. The model is
** provided solely on an "as is" basis. The entire risk as to its quality
** and performance is with the customer
*****************************************************************************
*
* This model is subject to change without notice. Texas Instruments
* Incorporated is not responsible for updating this model.
*
*****************************************************************************
*
** Released by: Texas Instruments Inc.
* Part: LM5146-Q1
* Date: 29JUL2019
* Model Type: TRANSIENT
* Simulator: PSPICE
* Simulator Version: 16.2.0.p001
* EVM Order Number: LM5146-Q1-EVM12V
* EVM Users Guide: SNVU591âNovember 2018
* Datasheet: SNVSAI4 - JUNE 2017
*
* Model Version: Final 1.20
* Topologies supported: Buck
*
*****************************************************************************
*
* Updates:
* Final 1.20
* Corrected syntax issue due to improper SUBCKT ending
*
* Final 1.10
* Removed dependency of SS parameter on EN_VOUT and VREF signals.
* This dependency was disabling UVLO feature in steadystate simulations.
*
* Final 1.00
* Release to Web.
*
*****************************************************************************
*
* Model Usage Notes:
*
* 1. The following features have been modeled
* a. Current limit and SYNC feature are implemented
* b. Maximum duty cycle, hard short response features are implemented
* 2. Temperature effects are not modeled.
*
*****************************************************************************
.SUBCKT LM5146-Q1_TRANS AGND BST COMP EN_UVLO EP EP2 FB HO ILIM LO NC1 NC2 PGND PGOOD
+ RT SS_TRK SW SYNCIN SYNCOUT VCC VIN
X_U4_U10 U4_N16967743 U4_N16854301 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=500E-3
X_U4_U71 SW U4_SW_FB BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=0.5 DELAY=5n
D_U4_D16 U4_N16854848 VDD D_D1
X_U4_S4 CLK AGND U4_N16854848 U4_N16855005 DRIVER_U4_S4
D_U4_D20 U4_N17097988 U4_ILIM_OVER_2P5 D_D2
X_U4_U61 U4_HO_LTCH U4_PRE_HO BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=0.5 DELAY=15n
X_U4_U74 POR STANDBY U4_N16855731 OR2_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=500E-3
I_U4_I2 AGND ILIM DC 100u
X_U4_U72 SW U4_ZXTH U4_N16855595 COMP_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=0.5
G_U4_ABMII8 U4_ZXTH AGND VALUE { LIMIT((V(U4_N16855005)*-50u),-0.5,1)
+ }
X_U4_U85 ILIM AGND U4_N16925242 U4_N16855421 COMPHYS_BASIC_GEN PARAMS:
+ VDD=1 VSS=0 VTHRESH=0.5
V_U4_V13 U4_N16925242 AGND 1m
V_U4_V16 U4_N16972977 AGND 2.5
X_U4_S5 U4_N16854801 AGND U4_N16855005 AGND DRIVER_U4_S5
X_U4_U42 U4_ILIM_OVER_2P5 U4_N16976073 U4_ILIM_SET N16979513
+ SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U4_U91 PWML U4_N17063432 INV_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=0.5 DELAY=25n
X_U4_U68 LO U4_LO_FB_B INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U4_U73 U4_EN_ILIMIT U4_N16855595 U4_N16855600 AND2_BASIC_GEN PARAMS:
+ VDD=1 VSS=0 VTHRESH=500E-3
G_U4_G2 AGND ILIM U4_N16855429 AGND 20u
X_U4_U38 U4_LO_LTCH U4_EN_ILIMIT U4_ILIM_COMP ILIMITX AND3_BASIC_GEN
+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U4_U18 STANDBY U4_N16854380 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=500E-3
I_U4_I1 VDD U4_N16854848 DC 250u
X_U4_U87 U4_BST_SW U4_N16958239 U4_N16957918 U4_BOOT_UVLO
+ COMPHYS2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 T=10
X_U4_U64 U4_PRE_HO U4_N16855352 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=500E-3
X_U4_U62 U4_N17063432 U4_N17063430 U4_N17067290 OR2_BASIC_GEN PARAMS:
+ VDD=1 VSS=0 VTHRESH=500E-3
X_U4_U88 ILIM U4_N16972977 U4_ILIM_OVER_2P5 COMP_BASIC_GEN PARAMS:
+ VDD=1 VSS=0 VTHRESH=0.5
X_U4_U57 U4_ILIM_OVER_2P5 U4_N17097988 BUF_DELAY_BASIC_GEN PARAMS:
+ VDD=1 VSS=0 VTHRESH=0.5 DELAY=20n
X_U4_U39 U4_HO_LTCH U4_N16854747 U4_N16854794 U4_N16854801
+ SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U4_U86 U4_N16950199 U4_N16878613 one_shot PARAMS: T=22
X_U4_U65 U4_LO_LTCH U4_PRE_LO BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=0.5 DELAY=15n
X_U4_U67 STANDBY U4_N16855600 U4_N16855640 OR2_BASIC_GEN PARAMS: VDD=1
+ VSS=0 VTHRESH=500E-3
X_U4_U69 U4_N16855005 U4_N16855433 BUF_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=0.5
X_U4_S6 U4_PRE_HO AGND BST HO DRIVER_U4_S6
X_U4_U43 U4_N17097988 U4_N16855731 U4_N16855429 N17102863
+ SRLATCHRHP_BASIC_GEN PARAMS: VDD=5 VSS=0 VTHRESH=0.5
X_U4_U81 U4_ENABLELO U4_N17067290 U4_LO_LTCH AND2_BASIC_GEN PARAMS:
+ VDD=1 VSS=0 VTHRESH=500E-3
C_U4_C4 U4_N16855005 AGND 4n
X_U4_U83 DEMBFLTR U4_N16855496 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=500E-3
V_U4_V14 U4_N16957918 AGND 0.13
X_U4_S12 U4_N16855352 AGND HO SW DRIVER_U4_S12
D_U4_D18 VCC BST D_D2
X_U4_U89 EN_VOUT U4_N16976073 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=500E-3
X_U4_U92 U4_N16855421 U4_ILIM_COMP INV_DELAY_BASIC_GEN PARAMS: VDD=1
+ VSS=0 VTHRESH=0.5 DELAY=20n
X_U4_U78 LO U4_EN_ILIMIT BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=0.5 DELAY=20n
V_U4_V15 U4_N16958239 AGND 3.75
X_U4_U30 U4_N16854461 U4_N16855433 U4_ENABLELO OR2_BASIC_GEN PARAMS:
+ VDD=1 VSS=0 VTHRESH=500E-3
X_U4_U90 U4_N17063432 U4_N17063430 one_shot PARAMS: T=90
R_U4_R8 U4_ZXTH U4_N16855517 1k
D_U4_D19 U4_EN_ILIMIT LO D_D2
X_U4_U9 U4_N16855640 U4_HO_LTCH U4_ZXL U4_N16854461
+ SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U4_U80 U4_N16854380 U4_SR_OUT U4_N16950199 AND2_BASIC_GEN PARAMS:
+ VDD=1 VSS=0 VTHRESH=500E-3
V_U4_V12 U4_N16855517 AGND -5m
X_U4_U66 U4_PRE_LO U4_N16855224 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=500E-3
X_U4_S13 U4_PRE_LO AGND U4_N16855274 LO DRIVER_U4_S13
C_U4_C5 U4_N16854794 AGND 4n
X_U4_U82 PWML U4_BOOT_UVLO U4_N16967743 AND2_BASIC_GEN PARAMS: VDD=1
+ VSS=0 VTHRESH=500E-3
X_U4_U33 STANDBY U4_N16855496 U4_N16854747 OR2_BASIC_GEN PARAMS: VDD=1
+ VSS=0 VTHRESH=500E-3
X_U4_U60 U4_SR_OUT U4_N16878613 U4_HO_LTCH OR2_BASIC_GEN PARAMS: VDD=1
+ VSS=0 VTHRESH=500E-3
E_U4_E1 U4_BST_SW AGND BST SW 1
X_U4_U8 U4_LO_FB_B U4_N16854301 U4_SR_OUT N16855463
+ SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U4_S14 U4_N16855224 AGND LO AGND DRIVER_U4_S14
E_U4_E3 U4_N16855274 AGND VCC AGND 1
D_U1_D7 U1_N16787350 COMP_CLAMP_CHG D_D2
E_U1_E5 U1_N16811554 AGND VREF U1_FB_EA 10000
V_U1_V2 U1_N16737804 U1_FB_EA 0.135
E_U1_E4 U1_N16787350 U1_RAMP_OFF VIN_INT AGND 6.6666m
V_U1_V5 U1_RAMP_OFF AGND 300m
X_U1_U3 EN_VOUT U1_N16689495 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=500E-3
D_U1_D8 COMP_CLAMP_CHG U1_N16787666 D_D2
R_U1_R4 SS_TRK VREF 10k
X_U1_S3 PWML AGND IRAMP U1_RAMP_OFF ERRORAMP_U1_S3
D_U1_D9 COMP_CLAMP_DISCHG U1_N16836988 D_D2
V_U1_V4 U1_N16787666 U1_N16787695 0.2
D_U1_D10 COMP U1_N16815648 D_D2
I_U1_I1 U1_N01140 SS_TRK DC 10u
E_U1_E3 U1_N16787695 COMP VIN_INT AGND 11.111111m
D_U1_D4 SS_TRK U1_N16737804 D_D2
X_U1_S4 VALLEY_PWM AGND COMP_CLAMP_DISCHG AGND ERRORAMP_U1_S4
C_U1_C3 IRAMP U1_RAMP_OFF 5p
X_U1_U4 POR HICCUPTIMEOUT U1_N16689495 STANDBY OR3_BASIC_GEN PARAMS:
+ VDD=1 VSS=0 VTHRESH=500E-3
V_U1_V1 U1_N01140 AGND 0.8
R_U1_R5 U1_N16811554 COMP 276
C_U1_C4 COMP_CLAMP_CHG AGND 5p
V_U1_V8 U1_N16815648 AGND 5
X_U1_F1 U1_N16836988 AGND COMP_CLAMP_CHG AGND ERRORAMP_U1_F1
C_U1_C2 COMP AGND 1u IC=0
D_U1_D6 U1_N168082641 COMP D_D2
X_U1_S2 STANDBY AGND SS_TRK AGND ERRORAMP_U1_S2
R_U1_R3 FB U1_FB_EA 1k
V_U1_V7 U1_N168082641 AGND 100m
X_U1_U5 IRAMP COMP_CLAMP_CHG COMP_CLAMP COMP_BASIC_GEN PARAMS: VDD=1
+ VSS=0 VTHRESH=0.5
D_U1_D5 U1_N167374381 U1_FB_EA D_D2
V_U1_V3 U1_N167374381 AGND 0.06
D_U1_D3 VREF U1_N01140 D_D2
X_U5_U86 U5_N16786127 U5_RESET U5_N16785473 U5_N16785488
+ SRLATCHSHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
R_U5_R9 U5_N16785903 AGND 20k
X_U5_S15 U5_N16785583 AGND U5_N16785384 AGND Oscillator_SYNC_U5_S15
X_U5_S16 U5_N16785745 AGND U5_IOSC_BOT AGND Oscillator_SYNC_U5_S16
E_U5_E4 U5_N16785923 AGND U5_N16785903 AGND 1
X_U5_U98 U5_N16785923 U5_N16786177 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=500E-3
X_U5_U81 U5_N16785488 POR U5_N16785438 OR2_BASIC_GEN PARAMS: VDD=1
+ VSS=0 VTHRESH=500E-3
X_U5_S17 U5_N16785438 AGND IOSC AGND Oscillator_SYNC_U5_S17
X_U5_U89 U5_N16785983 N16785815 U5_N16785923 VDD DEMBFLTR U5_GND_INV
+ DFFSBRB_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
C_U5_C8 U5_IOSC_BOT AGND 5p
X_U5_U82 U5_N16785863 U5_SYNCSET one_shot PARAMS: T=80
X_U5_U87 U5_N16786177 POR DEMBFLTR NOR2_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=500E-3
X_U5_U90 U5_N16786039 N16785842 U5_N16785983 U5_N16785923 DEMBFLTR
+ U5_GND_INV DFFSBRB_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
V_U5_V1 U5_N16792634 AGND 2
X_U5_U91 U5_N16785473 SYNCOUT INV_BASIC_GEN PARAMS: VDD=3 VSS=0
+ VTHRESH=500E-3
X_U5_U88 U5_N16785473 POR U5_N16785745 OR2_BASIC_GEN PARAMS: VDD=1
+ VSS=0 VTHRESH=500E-3
X_U5_U92 U5_N16785923 U5_N16786039 U5_N16785863 AND2_BASIC_GEN PARAMS:
+ VDD=1 VSS=0 VTHRESH=500E-3
X_U5_U93 U5_SET U5_N16785792 N16785380 U5_N16785583
+ SRLATCHSHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U5_U83 U5_IOSC_BOT VINBY30 U5_SET COMP_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=0.5
X_U5_U84 IOSC VINBY30 U5_RESET COMP_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=0.5
X_U5_U94 AGND U5_GND_INV INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=500E-3
E_U5_E3 U5_N16785792 AGND U5_SYNCSET AGND 1
G_U5_ABMII9 AGND U5_N16785384 VALUE { LIMIT((V(I_VIN_25_GND)*41.666m),0,7.5)}
X_U5_U99 SYNCIN U5_N16792634 U5_N16785903 COMP_BASIC_GEN PARAMS: VDD=1
+ VSS=0 VTHRESH=0.5
C_U5_C7 IOSC AGND 5p
X_U5_U85 U5_N16785473 CLK one_shot PARAMS: T=80
G_U5_ABMII10 AGND U5_IOSC_BOT VALUE { LIMIT(V(I_VIN_25_GND)*41.666m),0,7.5)}
X_U5_U95 U5_SYNCSET U5_N16786111 U5_N16786127 OR2_BASIC_GEN PARAMS:
+ VDD=1 VSS=0 VTHRESH=500E-3
X_U5_U80 U5_SET EN_VOUT U5_N16786111 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=500E-3
D_U5_D20 U5_N16785384 U5_IOSC_BOT D_D1
V_U3_V4 U3_N16800602 AGND 0.852
E_U3_E1 U3_N16682856 AGND VIN_INT AGND 1
R_U3_R2 U3_VINBY25 VINBY30 100
X_U3_U31 POR U3_N16802890 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=500E-3
X_U3_U14 U3_N16800195 U3_N16800229 BUF_DELAY_BASIC_GEN PARAMS: VDD=1
+ VSS=0 VTHRESH=0.5 DELAY=25u
V_U3_V1 U3_TEST AGND 1.2
V_U3_V7 U3_N16800294 AGND 24m
X_U3_U26 U3_N16763833 U3_N167719751 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=500E-3
X_U3_U22 U3_OV U3_N16800179 U3_UV U3_N16800211 OR3_BASIC_GEN PARAMS:
+ VDD=1 VSS=0 VTHRESH=500E-3
E_U3_ABM1 U3_N16682914 0 VALUE { IF(V(U3_VINBY25)<7.5, (V(U3_VINBY25)),
+ 7.5) }
D_U3_D3 U3_N16800524 U3_N16800209 D_D1
R_U3_R5 U3_N167719751 U3_N16771999 5
V_U3_V5 U3_N16800174 AGND 0.748
C_U3_C4 U3_N16771999 AGND 1n
X_U3_U20 POR U3_N16800185 U3_N16800179 OR2_BASIC_GEN PARAMS: VDD=1
+ VSS=0 VTHRESH=500E-3
V_U3_V6 U3_N16800223 AGND 24m
G_U3_ABMII1 AGND COMP_CLAMP_CHG VALUE {
+ LIMIT((V(I_VIN_25_GND)*8.3m),7.5,0) }
X_U3_U7 U3_N16691404 EN_UVLO_INT POR COMP_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=0.5
G_U3_ABMII2 AGND COMP_CLAMP_DISCHG VALUE {
+ LIMIT((V(I_VIN_25_GND)*16.7m),0,7.5) }
D_U3_D2 U3_N16800229 U3_N16800195 D_D1
X_U3_U17 U3_N16800207 U3_N16800558 BUF_DELAY_BASIC_GEN PARAMS: VDD=1
+ VSS=0 VTHRESH=0.5 DELAY=25u
D_U3_D5 U3_N16800558 U3_N16800207 D_D1
X_U3_U16 U3_N16800201 U3_N16800541 BUF_DELAY_BASIC_GEN PARAMS: VDD=1
+ VSS=0 VTHRESH=0.5 DELAY=25u
X_U3_U25 U3_N16772539 U3_N16771999 EN_VOUT N16769878
+ SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U3_U27 FB U3_N16800174 U3_N16800294 U3_N16800201 COMPHYS_BASIC_GEN
+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5
V_U3_V2 U3_N16691404 AGND 0.4
R_U3_R3 VINBY30 AGND 500
X_U3_U30 FB U3_N16800602 U3_N16800223 U3_N16800195 COMPHYS_BASIC_GEN
+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U3_U28 U3_N16800541 U3_N16800558 N16800586 U3_UV SRLATCHRHP_BASIC_GEN
+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5
R_U3_R1 U3_N16682856 U3_VINBY25 14.4k
X_U3_U12 U3_N16800195 U3_N16800209 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=500E-3
E_U3_ABM4 VCC 0 VALUE { IF(V(U3_N16802890)>0.5, 7.5,0) }
D_U3_D4 U3_N16800541 U3_N16800201 D_D1
C_U3_C3 U3_N16772539 AGND 1n IC=1
X_U3_H1 U3_N16682914 RT I_VIN_25_GND AGND HOUSE_KEEPING_U3_H1
X_U3_U3 EN_UVLO_INT U3_TEST U3_N16763833 COMP_BASIC_GEN PARAMS: VDD=1
+ VSS=0 VTHRESH=0.5
X_U3_U13 U3_N16800201 U3_N16800207 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=500E-3
X_U3_U15 U3_N16800209 U3_N16800524 BUF_DELAY_BASIC_GEN PARAMS: VDD=1
+ VSS=0 VTHRESH=0.5 DELAY=25u
X_U3_U21 EN_VOUT U3_N16800185 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=500E-3
G_U3_ABMII3 AGND IRAMP VALUE { LIMIT((V(I_VIN_25_GND)*83m),7.5,0) }
X_U3_U29 U3_N16800229 U3_N16800524 U3_OV N16800591 SRLATCHRHP_BASIC_GEN
+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_U3_ABM3 VDD 0 VALUE { IF(V(EN_VOUT)>0.5, 5,0) }
R_U3_R4 U3_N16763833 U3_N16772539 5
G_U3_ABMII4 AGND IOSC VALUE { LIMIT((V(I_VIN_25_GND)*83m),7.5,0) }
X_U3_S4 U3_N16800211 AGND PGOOD AGND HOUSE_KEEPING_U3_S4
E_E1 VIN_INT AGND VIN AGND 1
G_U6_G1 AGND U6_N16745668 U6_N16745614 AGND 0.02
X_U6_U26 U6_N16784881 U6_N16785284 INV_DELAY_BASIC_GEN PARAMS: VDD=1
+ VSS=0 VTHRESH=0.5 DELAY=10n
E_U6_ABM1 U6_N16745796 0 VALUE {
+ IF(V(U6_N16745696)>V(U6_N16745778),1,0) }
D_U6_D6 U6_N16746128 U6_N16746156 D_D2
D_U6_D5 U6_N16745668 U6_N16745696 D_D2
X_U6_U22 U6_N16784881 U6_N16785284 U6_N16784738 AND2_BASIC_GEN PARAMS:
+ VDD=1 VSS=0 VTHRESH=500E-3
X_U6_U25 U6_N16765692 CLK U6_N16783339 U6_N16784881 AND3_BASIC_GEN
+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
C_U6_C2 U6_N16746156 AGND 1n
X_U6_U27 CLK U6_N16787778 U6_8192CYCLE U6_N16746446 AND3_BASIC_GEN
+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
C_U6_C1 U6_N16745696 AGND 1n
X_U6_U16 U6_N16756861 POR U6_8192CYCLE_RESET OR2_BASIC_GEN PARAMS:
+ VDD=1 VSS=0 VTHRESH=500E-3
X_U6_U7 U6_N16746156 U6_N16746244 U6_8192CYCLE COMP_BASIC_GEN PARAMS:
+ VDD=1 VSS=0 VTHRESH=0.5
X_U6_U21 VALLEY_PWM U6_N16783339 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=500E-3
V_U6_V2 U6_N16746244 AGND 819.3
X_U6_U4 U6_N16745796 U6_N16746410 HICCUPTIMEOUT N16746044
+ SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
V_U6_V1 U6_N16745778 AGND 128
X_U6_U8 U6_8192CYCLE U6_N16756861 BUF_DELAY_BASIC_GEN PARAMS: VDD=1
+ VSS=0 VTHRESH=0.5 DELAY=50n
X_U6_U5 CLK HICCUPTIMEOUT U6_8192_START AND2_BASIC_GEN PARAMS: VDD=1
+ VSS=0 VTHRESH=500E-3
X_U6_U15 POR U6_8192CYCLE_RESET U6_N16746410 OR2_BASIC_GEN PARAMS:
+ VDD=1 VSS=0 VTHRESH=500E-3
X_U6_U18 HICCUPTIMEOUT U6_N16765692 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=500E-3
X_U6_S2 U6_8192CYCLE_RESET AGND U6_N16746156 AGND HICCUP_U6_S2
X_U6_U6 U6_8192_START U6_N16746074 one_shot PARAMS: T=50
X_U6_S1 U6_N16745882 AGND U6_N16745696 AGND HICCUP_U6_S1
X_U6_U17 STANDBY COMP_CLAMP U6_N16787778 OR2_BASIC_GEN PARAMS: VDD=1
+ VSS=0 VTHRESH=500E-3
X_U6_U1 U6_N16784738 U6_N16745614 one_shot PARAMS: T=50
X_U6_U28 U6_N16746446 STANDBY NPWM U6_N16745882 AND3_BASIC_GEN PARAMS:
+ VDD=1 VSS=0 VTHRESH=500E-3
G_U6_G2 AGND U6_N16746128 U6_N16746074 AGND 0.02
X_U2_U4 CLK U2_N16689730 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=500E-3
X_U2_U5 CLK U2_ILIMITX_N U2_N16690230 VALLEY_PWM SRLATCHRHP_BASIC_GEN
+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5
C_U2_C3 U2_N16690230 AGND 5p
X_U2_U2 CLK U2_N16695634 U2_N16688726 N16688771 SRLATCHRHP_BASIC_GEN
+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U2_U9 NPWM STANDBY COMP_CLAMP U2_N16695634 OR3_BASIC_GEN PARAMS:
+ VDD=1 VSS=0 VTHRESH=500E-3
X_U2_U3 U2_N16689730 U2_N16688726 U2_PWM AND2_BASIC_GEN PARAMS: VDD=1
+ VSS=0 VTHRESH=500E-3
X_U2_U7 ILIMITX U2_ILIMITX_N INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=500E-3
X_U2_U6 VALLEY_PWM U2_PWM PWML AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
+ VTHRESH=500E-3
X_U2_U10 IRAMP COMP NPWM COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_E2 EN_UVLO_INT AGND EN_UVLO AGND 1
.ENDS LM5146-Q1_TRANS
*$
.subckt DRIVER_U4_S4 1 2 3 4
S_U4_S4 3 4 1 2 _U4_S4
RS_U4_S4 1 2 1G
.MODEL _U4_S4 VSWITCH Roff=1e9 Ron=1m Voff=0.2 Von=0.8
.ends DRIVER_U4_S4
*$
.subckt DRIVER_U4_S5 1 2 3 4
S_U4_S5 3 4 1 2 _U4_S5
RS_U4_S5 1 2 1G
.MODEL _U4_S5 VSWITCH Roff=1e9 Ron=1m Voff=0.2 Von=0.8
.ends DRIVER_U4_S5
*$
.subckt DRIVER_U4_S6 1 2 3 4
S_U4_S6 3 4 1 2 _U4_S6
RS_U4_S6 1 2 1G
.MODEL _U4_S6 VSWITCH Roff=1e7 Ron=1.42 Voff=0.2 Von=0.8
.ends DRIVER_U4_S6
*$
.subckt DRIVER_U4_S12 1 2 3 4
S_U4_S12 3 4 1 2 _U4_S12
RS_U4_S12 1 2 1G
.MODEL _U4_S12 VSWITCH Roff=1e7 Ron=0.85 Voff=0.2 Von=0.8
.ends DRIVER_U4_S12
*$
.subckt DRIVER_U4_S13 1 2 3 4
S_U4_S13 3 4 1 2 _U4_S13
RS_U4_S13 1 2 1G
.MODEL _U4_S13 VSWITCH Roff=1e7 Ron=1.42 Voff=0.2 Von=0.8
.ends DRIVER_U4_S13
*$
.subckt DRIVER_U4_S14 1 2 3 4
S_U4_S14 3 4 1 2 _U4_S14
RS_U4_S14 1 2 1G
.MODEL _U4_S14 VSWITCH Roff=1e7 Ron=0.85 Voff=0.2 Von=0.8
.ends DRIVER_U4_S14
*$
.subckt ERRORAMP_U1_S3 1 2 3 4
S_U1_S3 3 4 1 2 _U1_S3
RS_U1_S3 1 2 1G
.MODEL _U1_S3 VSWITCH Roff=1e9 Ron=10 Voff=0.8 Von=0.2
.ends ERRORAMP_U1_S3
*$
.subckt ERRORAMP_U1_S4 1 2 3 4
S_U1_S4 3 4 1 2 _U1_S4
RS_U1_S4 1 2 1G
.MODEL _U1_S4 VSWITCH Roff=100e6 Ron=1 Voff=0.2 Von=0.8
.ends ERRORAMP_U1_S4
*$
.subckt ERRORAMP_U1_F1 1 2 3 4
F_U1_F1 3 4 VF_U1_F1 1
VF_U1_F1 1 2 0V
.ends ERRORAMP_U1_F1
*$
.subckt ERRORAMP_U1_S2 1 2 3 4
S_U1_S2 3 4 1 2 _U1_S2
RS_U1_S2 1 2 1G
.MODEL _U1_S2 VSWITCH Roff=1e9 Ron=12 Voff=0.2 Von=0.8
.ends ERRORAMP_U1_S2
*$
.subckt Oscillator_SYNC_U5_S15 1 2 3 4
S_U5_S15 3 4 1 2 _U5_S15
RS_U5_S15 1 2 1G
.MODEL _U5_S15 VSWITCH Roff=1e9 Ron=1 Voff=0.2 Von=0.8
.ends Oscillator_SYNC_U5_S15
*$
.subckt Oscillator_SYNC_U5_S16 1 2 3 4
S_U5_S16 3 4 1 2 _U5_S16
RS_U5_S16 1 2 1G
.MODEL _U5_S16 VSWITCH Roff=1e9 Ron=10 Voff=0.2 Von=0.8
.ends Oscillator_SYNC_U5_S16
*$
.subckt Oscillator_SYNC_U5_S17 1 2 3 4
S_U5_S17 3 4 1 2 _U5_S17
RS_U5_S17 1 2 1G
.MODEL _U5_S17 VSWITCH Roff=1e9 Ron=10 Voff=0.2 Von=0.8
.ends Oscillator_SYNC_U5_S17
*$
.subckt HOUSE_KEEPING_U3_H1 1 2 3 4
H_U3_H1 3 4 VH_U3_H1 1
VH_U3_H1 1 2 0V
.ends HOUSE_KEEPING_U3_H1
*$
.subckt HOUSE_KEEPING_U3_S4 1 2 3 4
S_U3_S4 3 4 1 2 _U3_S4
RS_U3_S4 1 2 1G
.MODEL _U3_S4 VSWITCH Roff=1e9 Ron=50 Voff=0.2 Von=0.8
.ends HOUSE_KEEPING_U3_S4
*$
.subckt HICCUP_U6_S2 1 2 3 4
S_U6_S2 3 4 1 2 _U6_S2
RS_U6_S2 1 2 1G
.MODEL _U6_S2 VSWITCH Roff=1e9 Ron=10m Voff=0.0V Von=1.0V
.ends HICCUP_U6_S2
*$
.subckt HICCUP_U6_S1 1 2 3 4
S_U6_S1 3 4 1 2 _U6_S1
RS_U6_S1 1 2 1G
.MODEL _U6_S1 VSWITCH Roff=1e9 Ron=10m Voff=0.0V Von=1.0V
.ends HICCUP_U6_S1
*$
.SUBCKT AND2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE YINT 0 VALUE {IF(V(A) > {VTHRESH} & V(B) > {VTHRESH},{VDD},{VSS})}
RINT YINT Y 1
CINT Y 0 1n
.ENDS AND2_BASIC_GEN
*$
.SUBCKT AND4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE YINT 0 VALUE {IF(V(A) > {VTHRESH} & V(B) > {VTHRESH} & V(C) > {VTHRESH} & V(D) > {VTHRESH},{VDD},{VSS})}
RINT YINT Y 1
CINT Y 0 1n
.ENDS AND4_BASIC_GEN
*$
.SUBCKT NAND3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE YINT 0 VALUE {IF(V(A) > {VTHRESH} & V(B) > {VTHRESH} & V(C) > {VTHRESH},{VSS},{VDD})}
RINT YINT Y 1
CINT Y 0 1n
.ENDS NAND3_BASIC_GEN
*$
.SUBCKT NAND4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE YINT 0 VALUE {IF(V(A) > {VTHRESH} & V(B) > {VTHRESH} & V(C) > {VTHRESH} & V(D) > {VTHRESH},{VSS},{VDD})}
RINT YINT Y 1
CINT Y 0 1n
.ENDS NAND4_BASIC_GEN
*$
.SUBCKT OR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE YINT 0 VALUE {IF(V(A) > {VTHRESH} | V(B) > {VTHRESH},{VDD},{VSS})}
RINT YINT Y 1
CINT Y 0 1n
.ENDS OR2_BASIC_GEN
*$
.SUBCKT OR3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE YINT 0 VALUE {IF(V(A) > {VTHRESH} | V(B) > {VTHRESH} | V(C) > {VTHRESH},{VDD},{VSS})}
RINT YINT Y 1
CINT Y 0 1n
.ENDS OR3_BASIC_GEN
*$
.SUBCKT OR4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE YINT 0 VALUE {IF(V(A) > {VTHRESH} |V(B) > {VTHRESH} | V(C) > {VTHRESH} |V(D) > {VTHRESH},{VDD},{VSS})}
RINT YINT Y 1
CINT Y 0 1n
.ENDS OR4_BASIC_GEN
*$
.SUBCKT NOR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE YINT 0 VALUE {IF(V(A) > {VTHRESH} | V(B) > {VTHRESH},{VSS},{VDD})}
RINT YINT Y 1
CINT Y 0 1n
.ENDS NOR2_BASIC_GEN
*$
.SUBCKT NOR3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE YINT 0 VALUE {IF(V(A) > {VTHRESH} | V(B) > {VTHRESH} | V(C) > {VTHRESH},{VSS},{VDD})}
RINT YINT Y 1
CINT Y 0 1n
.ENDS NOR3_BASIC_GEN
*$
.SUBCKT NOR4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE YINT 0 VALUE {IF(V(A) > {VTHRESH} | V(B) > {VTHRESH} | V(C) > {VTHRESH} |V(D) > {VTHRESH},{VSS},{VDD})}
RINT YINT Y 1
CINT Y 0 1n
.ENDS NOR4_BASIC_GEN
*$
.SUBCKT NOR5_BASIC_GEN A B C D E Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE YINT 0 VALUE {IF(V(A) > {VTHRESH} |V(B) > {VTHRESH} | V(C) > {VTHRESH} | V(D) > {VTHRESH} | V(E) > {VTHRESH},{VSS},{VDD})}
RINT YINT Y 1
CINT Y 0 1n
.ENDS NOR5_BASIC_GEN
*$
.SUBCKT NOR6_BASIC_GEN A B C D E F Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} | V(B) > {VTHRESH} | V(C) > {VTHRESH} | V(D) > {VTHRESH} | V(E) > {VTHRESH} |V(F) > {VTHRESH},{VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS NOR6_BASIC_GEN
*$
.SUBCKT INV_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE YINT 0 VALUE {IF(V(A) > {VTHRESH} ,{VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1p
.ENDS INV_BASIC_GEN
*$
.SUBCKT XOR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE YINT 0 VALUE {IF(V(A) > {VTHRESH} ^ V(B) > {VTHRESH},{VDD},{VSS})}
RINT YINT Y 1
CINT Y 0 1n
.ENDS XOR2_BASIC_GEN
*$
.SUBCKT XNOR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE YINT 0 VALUE {IF(V(A) > {VTHRESH} ^ V(B) > {VTHRESH},{VSS},{VDD})}
RINT YINT Y 1
CINT Y 0 1n
.ENDS XNOR2_BASIC_GEN
*$
.SUBCKT INV_DELAY_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n
E_ABMGATE1 YINT1 0 VALUE {{IF(V(A) > {VTHRESH} ,
+ {VDD},{VSS})}}
RINT YINT1 YINT2 1
CINT YINT2 0 {DELAY*1.3}
E_ABMGATE2 YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} ,
+ {VSS},{VDD})}}
RINT2 YINT3 Y 1
CINT2 Y 0 1n
.ENDS INV_DELAY_BASIC_GEN
*$
.SUBCKT BUF_DELAY_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n
E_ABMGATE1 YINT1 0 VALUE {{IF(V(A) > {VTHRESH} ,
+ {VDD},{VSS})}}
RINT YINT1 YINT2 1
CINT YINT2 0 {DELAY*1.3}
E_ABMGATE2 YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} ,
+ {VDD},{VSS})}}
RINT2 YINT3 Y 1
CINT2 Y 0 1n
.ENDS BUF_DELAY_BASIC_GEN
*$
.SUBCKT BUF_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} ,
+ {VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS BUF_BASIC_GEN
*$
.SUBCKT SRLATCHSHP_BASIC_GEN S R Q QB PARAMS: VDD=1 VSS=0 VTHRESH=0.5
GQ 0 Qint VALUE = {IF(V(S) > {VTHRESH},5,IF(V(R)>{VTHRESH},-5, 0))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D1
V1 MY5 0 {VDD}
D_D11 MYVSS Qint D_D1
V2 MYVSS 0 {VSS}
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr QB 1
Cdummy1 Q 0 1n
Cdummy2 QB 0 1n
.IC V(Qint) {VSS}
.ENDS SRLATCHSHP_BASIC_GEN
*$
.SUBCKT SRLATCHRHP_BASIC_GEN S R Q QB PARAMS: VDD=1 VSS=0 VTHRESH=0.5
GQ 0 Qint VALUE = {IF(V(R) > {VTHRESH},-5,IF(V(S)>{VTHRESH},5, 0))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D1
V1 MY5 0 {VDD}
D_D11 MYVSS Qint D_D1
V2 MYVSS 0 {VSS}
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr QB 1
Cdummy1 Q 0 1n
Cdummy2 QB 0 1n
.IC V(Qint) {VSS}
.ENDS SRLATCHRHP_BASIC_GEN
*$
.SUBCKT SBRBLATCHRHP_BASIC_GEN SB RB Q QB PARAMS: VDD=1 VSS=0 VTHRESH=0.5
GQ 0 Qint VALUE = {IF(V(RB) < {VTHRESH},-5,IF(V(SB) < {VTHRESH},5, 0))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D2
V1 MY5 0 {VDD}
D_D11 MYVSS Qint D_D2
V2 MYVSS 0 {VSS}
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr QB 1
.IC V(Qint) {VSS}
.ENDS SBRBLATCHRHP_BASIC_GEN
*$
.SUBCKT SBRBLATCHSHP_BASIC_GEN SB RB Q QB PARAMS: VDD=1 VSS=0 VTHRESH=0.5
GQ 0 Qint VALUE = {IF(V(SB) < {VTHRESH},5,IF(V(RB) < {VTHRESH},-5, 0))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D2
V1 MY5 0 {VDD}
D_D11 MYVSS Qint D_D2
V2 MYVSS 0 {VSS}
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr QB 1
.IC V(Qint) {VSS}
.ENDS SBRBLATCHSHP_BASIC_GEN
*$
.SUBCKT DFFSBRB_SHPBASIC_GEN Q QB CLK D RB SB PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X1 CLK CLKdel INV_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 15n
X2 CLK CLKdel CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}
GQ 0 Qint VALUE = {IF(V(SB) < {VTHRESH},5,IF(V(RB)<{VTHRESH},-5, IF(V(CLKint)> {VTHRESH},
+ IF(V(D)> {VTHRESH},5,-5),0)))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D2
V1 MY5 0 {VDD}
D_D11 MYVSS Qint D_D2
V2 MYVSS 0 {VSS}
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 20n
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr Qb 1
Cdummy1 Q 0 1nF
Cdummy2 QB 0 1nF
.IC V(Qint) {VSS}
.ENDS DFFSBRB_SHPBASIC_GEN
*$
.SUBCKT DFFSR_SHPBASIC_GEN Q QB CLK D R S PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X1 CLK CLKdel INV_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 15n
X2 CLK CLKdel CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}
GQ 0 Qint VALUE = {IF(V(S) > {VTHRESH},5,IF(V(R) > {VTHRESH},-5, IF(V(CLKint)> {VTHRESH},
+ IF(V(D)> {VTHRESH},5,-5),0)))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D2
V1 MY5 0 {VDD}
D_D11 MYVSS Qint D_D2
V2 MYVSS 0 {VSS}
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 20n
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr Qb 1
Cdummy1 Q 0 1nF
Cdummy2 QB 0 1nF
.IC V(Qint) {VSS}
.ENDS DFFSR_SHPBASIC_GEN
*$
.SUBCKT DFFSBRB_RHPBASIC_GEN Q QB CLK D RB SB PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X1 CLK CLKdel INV_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 15n
X2 CLK CLKdel CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}
GQ 0 Qint VALUE = {IF(V(RB) < {VTHRESH},-5,IF(V(SB)< {VTHRESH},5, IF(V(CLKint)> {VTHRESH},
+ IF(V(D)> {VTHRESH},5,-5),0)))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D1
V1 MY5 0 5
D_D11 0 Qint D_D1
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 20n
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr Qb 1
Cdummy1 Q 0 1nF
Cdummy2 QB 0 1nF
.IC V(Qint) {VSS}
.ENDS DFFSBRB_RHPBASIC_GEN
*$
.SUBCKT DFFSR_RHPBASIC_GEN Q QB CLK D R S PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X1 CLK CLKdel INV_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 15n
X2 CLK CLKdel CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}
GQ 0 Qint VALUE = {IF(V(R) > {VTHRESH},-5,IF(V(S) > {VTHRESH},5, IF(V(CLKint)> {VTHRESH},
+ IF(V(D)> {VTHRESH},5,-5),0)))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D2
V1 MY5 0 {VDD}
D_D11 MYVSS Qint D_D2
V2 MYVSS 0 {VSS}
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 20n
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr Qb 1
Cdummy1 Q 0 1nF
Cdummy2 QB 0 1nF
.IC V(Qint) {VSS}
.ENDS DFFSR_RHPBASIC_GEN
*$
.model NMOS02 NMOS
+ VTO = 2.5
+ KP = 0.8
+ LAMBDA = 0.001
*$
.model NMOS01 NMOS
+ VTO = 2
+ KP = 0.5555
+ LAMBDA = 0.001
*$
.model PMOS01 PMOS
+ VTO = -2
+ KP = .889
+ LAMBDA = 0.001
*$
.SUBCKT FALLING_DELAY IN OUT PARAMS: DELAY=100n VDD=1 VSS=0 VTHRESH=0.5
X_U1 INT OUT BUF_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH=
+ {VTHRESH}
R_R1 IN INT {DELAY/(0.693 * 1E-9)}
C_C1 0 INT 1n
D_D11 IN INT DD
.MODEL DD D( IS=1F N=0.01 TT = 10p )
.ENDS FALLING_DELAY
*$
.SUBCKT Z_IDEAL A C PARAMS: RS = 1 VTH = 6.4
G1 A C VALUE { MIN(0, ( V(A) - V(C) + { VTH } ) / { RS } ) }
R1 A C 1G
.ENDS Z_IDEAL
*$
.SUBCKT COMPHYS_BASIC_GEN INP INM HYS OUT PARAMS: VDD=1 VSS=0 VTHRESH=0.5
EIN INP1 INM1 INP INM 1
EHYS INP1 INP2 VALUE { IF( V(1) > {VTHRESH},-V(HYS),0) }
EOUT OUT 0 VALUE { IF( V(INP2)>V(INM1), {VDD} ,{VSS}) }
R1 OUT 1 1
C1 1 0 5n
RINP1 INP1 0 1K
.ENDS COMPHYS_BASIC_GEN
*$
.SUBCKT AND3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE Y 0 VALUE {IF(V(A) > {VTHRESH} & V(B) > {VTHRESH} & V(C) > {VTHRESH},{VDD},{VSS})}}
.ENDS AND3_BASIC_GEN
*$
.SUBCKT COMP_BASIC_GEN INP INM Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABM Yint 0 VALUE {IF (V(INP) > + V(INM), {VDD},{VSS})}
R1 Yint Y 1
C1 Y 0 1n
.ENDS COMP_BASIC_GEN
*$
.SUBCKT MUX2_BASIC_GEN A B S Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE YINT 0 VALUE {{IF(V(S) > {VTHRESH}, V(B),V(A))}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS MUX2_BASIC_GEN
*$
.subckt Var_Resistor_HIGH IN VCC GND O+ O-
E_RVAL RVAL GND VALUE={(0.03787*V(VCC)*V(VCC)-1.02313*V(VCC)+13.2713)*(1-V(IN)) + V(IN)*1e6}
R_ERVAL RVAL GND 1G
G_R O+ O- VALUE={V(O+,O-)/(V(RVAL))}
ROUT O+ O- 1G
.ENDS
*$
.subckt Var_Resistor_LOW IN VCC GND O+ O-
E_RVAL RVAL GND VALUE={(0.0303*V(VCC)*V(VCC)-0.728*V(VCC)+11.0737)*V(IN)+ (1-V(IN))*1e6}
R_ERVAL RVAL GND 1G
G_R O+ O- VALUE={V(O+,O-)/(V(RVAL))}
ROUT O+ O- 1G
.ENDS
*$
.subckt Var_Resistor_PROP VCC GND O+ O-
E_RVAL RVAL GND VALUE={0.3206*V(VCC)*V(VCC)-7.696*V(VCC)+70.963}
R_ERVAL RVAL GND 1G
G_R O+ O- VALUE={V(O+,O-)/(V(RVAL))}
ROUT O+ O- 1G
.ENDS
*$
.SUBCKT LM3414Q1 D G S Bulk
M1x D G S Bulk LM3414Q1
.MODEL LM3414Q1 NMOS Level=1 CBD=26.5p CBS=31.8p CGBO=142n
+ CGDO=640n CGSO=768n GAMMA=1.59 IS=250f KP=0.968
+ LAMBDA=0.116 MJ=0.460 PB=0.800 PHI=.75 RD=0.108 RS=0.108
+ VTO=2
.ENDS
*$
.SUBCKT NMOS_1 D G S B PARAMS: L=1U W=1U
M1 D G S B DMOS L=1U W=1U
.MODEL DMOS NMOS(LEVEL=3 VMAX=625k THETA=900m
+ ETA=2.00m VTO=2 KP=107 lambda=0.01
.ENDS
*$
.SUBCKT D_IDEAL A C PARAMS: RS = 1 VTH = 0.7
G1 A C VALUE { MAX(0, ( V(A) - V(C) - { VTH }) / { RS } ) }
R1 A C 1G
.ENDS D_IDEAL
*$
.model DIODE01 D
+ IS = 1E-15
+ N = 1
+ TT = 1E-11
+ RS = 0.5
+ CJO = 1E-10
+ XTI = 0.0
*$
.SUBCKT DELAY INP OUT PARAMS: RINP = 1k DELAY = 10n
R1 INP 101 {RINP}
C1 101 102 { 1.4427 * DELAY / RINP }
E1 102 0 OUT 0 0.5
E2 OUT 0 VALUE {IF(V(101) > 0.5, 1, 0)}
.ENDS DELAY
*$
.SUBCKT COMP VOUT VINP VINN PARAMS: VHYS = 0.05
E1 YINT 0 VALUE {IF(V(VINP) + V(VOUT)*VHYS > V(VINN), 1, 0)}
R1 YINT VOUT 1
C1 VOUT 0 1n
.ENDS COMP
*$
.SUBCKT COMP_INV VOUT VINP VINN PARAMS: VHYS = 0.05
E1 YINT 0 VALUE {IF(V(VINP) + (1 - V(VOUT))*VHYS > V(VINN), 0, 1)}
R1 YINT VOUT 1
C1 VOUT 0 1n
.ENDS COMP_INV
*$
.SUBCKT OP_AMP P M OUT
+ PARAMs: Hlimit=5 Rin=10Meg BW=18Meg DC_Gain=100 Rout=100 Llimit=0 SRP=1 SRM=1
R_Rin P M {Rin}
E_E1 5 0 M P {-Gain}
E_LIMIT2 6 0 VALUE {LIMIT(V(5), {-Abs(SRM)*Ca*1Meg+V(1)/Ra},
+ {SRP*Ca*1Meg+V(1)/Ra})}
G_G2 1 0 6 0 -1
R_Ra 0 1 {Ra}
C_Ca 0 1 {Ca}
E_LIMIT1 2 0 VALUE {LIMIT(V(1),{Llimit},{Hlimit})}
V_VL 3 0 {Llimit+200m}
V_VH 4 0 {Hlimit-200m}
D_D1 3 1 Dideal
D_D2 1 4 Dideal
R_Rout OUT 2 {Rout}
.model Dideal D Is=1e-10 Cjo=.01pF Rs=1m N=1
.PARAM Ra=1k Ca={exp(DC_gain*log(10)/20)/(2*3.14159*BW*Ra)}
+ Gain={exp(DC_gain*log(10)/20)/Ra}
.ENDS OP_AMP
*$
.subckt one_shot in out params: t=100
s_s1 meas 0 reset2 0 s1
e_abm1 ch 0 value { if( v(in)>0.5 | v(out)>0.5,1,0) }
r_r2 reset2 reset 0.1
e_abm3 out 0 value { if( v(meas)<0.5 & v(ch)>0.5,1,0) }
r_r1 meas ch {t}
c_c2 0 reset2 1.4427n
c_c1 0 meas 1.4427n
e_abm2 reset 0 value { if(v(ch)<0.5,1,0) }
.model s1 vswitch
+ roff=1e+009
+ ron=1
+ voff=0.25
+ von=0.75
.ends one_shot
*$
.SUBCKT COMPHYS2_BASIC_GEN INP INM HYS OUT PARAMS: VDD=1 VSS=0 VTHRESH=0.5
+ T=10
EIN INP1 INM1 INP INM 1
EHYS INM2 INM1 VALUE { IF( V(1) > {VTHRESH},-V(HYS)/2,V(HYS)/2) }
EOUT OUT 0 VALUE { IF( V(INP1)>V(INM2), {VDD} ,{VSS}) }
R1 OUT 1 1
C1 1 0 {T*1e-9}
RINP1 INP1 0 10K
RINM2 INM2 0 10K
.ENDS COMPHYS2_BASIC_GEN
*$
.SUBCKT BUFFER_PS A Y PARAMS: vhi=1 vlo=0 vthresh=500e-3 tplh=1e-9
+ tphl=1e-9 tr=1e-9 tf=1e-9
RA A 0 1e11
CA A 0 0.01pF
VS VSUP 0 DC 1
EBUF1 Ypp 0 VALUE={IF(V(A) > ({vthresh}), 1, 0)}
ROUTpp Ypp 0 1e11
XNSW1 OUTp Ypp 0 NSW_PS PARAMS: RONval={(tplh+1e-15)/(1e-12*0.693)}
+ VTHval=0.5
XPSW1 OUTp Ypp VSUP PSW_PS PARAMS: RONval={(tphl+1e-15)/(1e-12*0.693)}
+ VTHval=0.5
CDEL1 OUTp 0 1pF
ETHRESH Yp 0 VALUE={IF(V(OUTp) > 0.5, 1, 0)}
ROUTp Yp 0 1e11
XNSW2 OUTr Yp 0 NSW_PS PARAMS: RONval={(tf+1e-15)/(1e-12*2.3)} VTHval=0.5
XPSW2 OUTr Yp VSUP PSW_PS PARAMS: RONval={(tr+1e-15)/(1e-12*2.3)} VTHval=0.5
CDEL2 OUTr 0 1pF
EOUT OUTf 0 VALUE={V(OUTr)*({vhi} - {vlo})+{vlo}}
RDR OUTf Y 1000
RO Y 0 1e11
.ENDS BUFFER_PS
*$
.SUBCKT INV_PS Y A PARAMS: vhi=1 vlo=0 vthresh=500e-3
+ tplh=1e-9 tphl=1e-9 tr=1e-9 tf=1e-9
RA A 0 1e11
CA A 0 0.01pF
VS VSUP 0 DC 1
EINV1 Ypp 0 VALUE={IF(V(A) > ({vthresh}), 0, 1)}
ROUTpp Ypp 0 1e11
XNSW1 OUTp Ypp 0 NSW_PS PARAMS: RONval={(tplh+1e-15)/(1e-12*0.693)}
+ VTHval=0.5
XPSW1 OUTp Ypp VSUP PSW_PS PARAMS: RONval={(tphl+1e-15)/(1e-12*0.693)}
+ VTHval=0.5
CDEL1 OUTp 0 1pF
ETHRESH Yp 0 VALUE={IF(V(OUTp) > 0.5, 1, 0)}
ROUTp Yp 0 1e11
XNSW2 OUTr Yp 0 NSW_PS PARAMS: RONval={(tf+1e-15)/(1e-12*2.3)} VTHval=0.5
XPSW2 OUTr Yp VSUP PSW_PS PARAMS: RONval={(tr+1e-15)/(1e-12*2.3)} VTHval=0.5
CDEL2 OUTr 0 1pF
EOUT OUTf 0 VALUE={V(OUTr)*({vhi} - {vlo})+{vlo}}
RDR OUTf Y 1000
RO Y 0 1e11
.ENDS INV_PS
*$
.model D_D1 d
+ is=1e-015
+ tt=10p
+ rs=0.005
+ n=0.01
*$
.model D_D2 d
+ is=1e-015
+ tt=10p
+ rs=0.005
+ n=0.001
*$
.model D_D3 d
+ is=1e-015
+ tt=10p
+ rs=0.05
+ n=0.01
*$
.SUBCKT LDCR IN OUT
+ PARAMs: L=1u DCR=0.01 IC=0
L IN 1 {L} IC={IC}
RDCR 1 OUT {DCR}
.ENDS LDCR
*$
.SUBCKT CESR IN OUT
+ PARAMs: C=100u ESR=0.01 X=2 IC=0
C IN 1 {C*X} IC={IC}
RESR 1 OUT {ESR/X}
.ENDS CESR
*$

UCC25800-Q1: Power Loss Calculation

zhexi zhang — Fri, 05 Jun 2026 03:33:57 GMT

Part Number: UCC25800-Q1

Hi, TI college

Here is our product using the UCC25800-q1 circuit electrical diagram.

Now, we wonder the Power Loss of this circuit working on this condition.

Can you provide some accurate ways to calculate power losses.

IF you have any questions about the working condition, it's fine to ask for more information!

DAC39RF10-OUTPUT-FULLSCALE-CALC: IBIS-AMI Model for DAC39RF20

John Carder — Thu, 04 Jun 2026 15:00:42 GMT

Part Number: DAC39RF10-OUTPUT-FULLSCALE-CALC
Other Parts Discussed in Thread: DAC39RF20

Is there an IBIS-AMI Model for DAC39RF20 to simulate its High-Speed interface?

PSPICE-FOR-TI: Activation Error

Mitsuru Tsuruta — Thu, 04 Jun 2026 06:23:33 GMT

Part Number: PSPICE-FOR-TI

I bought a new PC and tried to install PSpice for TI again, but I couldn’t install it because I’ve reached the installation limit.
I’ve already uninstalled PSpice for TI from my old PC.
Could you please delete the old account information so I can use PSpice for TI on my new PC?

TPSM81033: Need cadence 17.2/4 version CAD file

Praveendhaya Dhayalan — Thu, 04 Jun 2026 06:20:08 GMT

Part Number: TPSM81033

It seems complex design IC & few of calculation not able to calculate to create a pad satck, Kinldy provide the CAD file(Allegro cadence 17.2/17.4 Version)

LM5156HEVM-FLY: Technical Support

Balaji B — Thu, 04 Jun 2026 05:22:02 GMT

Part Number: LM5156HEVM-FLY

Right now I'd planned to procure this development board for my application. I'm planning to change the diodes and transformers in such a way that it can produce 28V output and power rating of 33W. If I'm facing any issues can i get any assistance or support from TI

TPS63710: I am unable to download the PSpice model for the TPS63710.

Takahiro Ishioka — Thu, 04 Jun 2026 02:09:20 GMT

Part Number: TPS63710

When I attempt to obtain the [TPS63710 Unencrypted PSpice Transient Model Package (Rev. C)] from the link below, an ERROR404 message is displayed.

https://www.ti.com/product/ja-jp/TPS63710?utm_source=google&utm_medium=cpc&utm_campaign=app-null-null-gpn_jp-cpc-pf-google-jp_jp_cons&utm_content=TPS63710&ds_k=TPS63710&DCM=yes&gclsrc=aw.ds&gad_source=1&gad_campaignid=20279248515&gclid=EAIaIQobChMIvpTpsbnslAMVorspAx1zUQrvEAAYASAAEgJdyPD_BwE#all

I would like to request the PSpice model for the TPS63710.

TMS320C6416: IBIS for TMS320C6416

Kenneth Kosin — Wed, 03 Jun 2026 13:34:53 GMT

Part Number: TMS320C6416

I am looking for an IBIS model to perform a Hyperlynx simulation for the TMS320C6416.

LMK04208: TICSPro 1.7.10.1 has problems loading .tcs files on part LMK04208

Simon Stephany — Wed, 03 Jun 2026 11:22:57 GMT

Part Number: LMK04208

TICSPro 1.7.10.1 has problems loading .tcs files with part LMK04208. The imported values are garbage and if the register values are imported after that even they are not correctly loaded and the first register is altered on import.

CCSTUDIO-THEIA: Can't find compiler for MSP432P401R in CCS 20.5.1.12__1.11.1

Xu Fei — Wed, 03 Jun 2026 05:27:19 GMT

Part Number: CCSTUDIO-THEIA
Other Parts Discussed in Thread: MSP432WARE, ARM-CGT

Hi,

I installed CCS 20.5.1.12__1.11.1, and my local compiler list folder is like this:

in C:\ti\ccs2051\ccs\tools\compiler

There is only compiler for msp430, but not msp432.

When I use CCS to import the example from msp432ware:

C:\ti\msp432ware\MSP432Ware_3_50_00_02\examples\boards\MSP-EXP432P401R\MSP-EXP432P401R_Software_Examples\Firmware\Source\BlinkLED_MSP432P401R

The CCS has an error:

Problems importing projects: No TI Arm compilers, supporting device 'MSP432P401R', are currently installed.

I would like to see how to install the TI Arm compiler for msp432 in CCS ?

I guess I have 2 options,

www.ti.com/.../ARM-CGT

but I have checked that, the ARM-CGT and ARM-CGT-CLANG both supports only CCxxx MCUs, no MSPxxx MCUs, like this:

2. www.ti.com/.../1.02.00.01

but the gcc compiler seems to be a standalone compiler, I'm not sure if it works together with CCS.

Any solutions?

Thanks.

PSPICE-FOR-TI: LM74910H-Q1 PSpice Simulation

Kazuki Itoh — Wed, 03 Jun 2026 01:50:43 GMT

Part Number: PSPICE-FOR-TI
Other Parts Discussed in Thread: LM74910H-Q1

Hi team,

The customer is currently attempting to simulate the LM74910H-Q1 in PSpice for TI for preliminary validation as part of their evaluation process. However, they are encountering the same error in both the sample project for the LM74910H-Q1 and their custom circuit using this model when running the simulation. They would appreciate your guidance on the following points.

Model Used: They used the LM74910H model found via PSpice Part Search in PSpice for TI.

The sample obj file was downloaded from the following link within the Testbenches section of the above model: https://software-dl.ti.com/pspice/esd/models/LM74910H_V3.0.zip

Issue Description: When executing PSpice, the simulation stops with the following error:

ERROR(ORPSIM-15108): Subcircuit 74AC161 used by X_U6.X_HGATE_CTRL.X_U1000A is undefined

Similar errors also occur for: X_U6.X_HGATE_CTRL.X_U1001A X_U6.X_HGATE_CTRL.X_U1000B X_U6.X_HGATE_CTRL.X_U1001B

Verified Content: Sample project: LM74910H-Q1_TRANS

Environment: PSpice for TI 23.1.0 (30 January 2024)

The following libraries are loaded during simulation: LM74910H.lib nom.lib nom_pspti.lib

The LM74910H.lib itself loads normally, and index file generation is confirmed in the execution log. However, the simulation stops immediately after with the 74AC161 undefined error.

Additional Notes: When opening the sample project in PSpice for TI 23.1, the following message was also displayed: INFO(ORCAP-2459): TI model libraries have been updated to the latest version in this design.

Therefore, they suspect that in the current PSpice for TI 23.1 environment, the dependent library for 74AC161 required internally by the LM74910H-Q1 model may be missing, or there may be a compatibility issue after the library update.

Questions for Confirmation: They saw in another E2E thread that the paid PSpice Full Version is required—is this true? Are there any additional dependent libraries required to run the LM74910H-Q1 PSpice model in PSpice for TI 23.1? If so, could you provide them?

Best regards,
Kazuki Itoh

PSPICE-FOR-TI: Unable to Launch OrCAD PSpice for TI – License Error ORCOMMN-12005

Supriya K S — Tue, 02 Jun 2026 14:47:22 GMT

Part Number: PSPICE-FOR-TI

Dear TI Support Team,

I am facing an issue while using PSpice for TI.

When I use it first time after installing completely, its working. But when I close the software once and try to launch it again, I receive the following error message:

"ERROR(ORCOMMN-12005): Unable to launch OrCAD PSpice TI. A valid license was not found at the license server. Update the license server configuration to include OrCAD PSpice TI licenses."

Details:

Software: PSpice for TI
Operating System: Windows 10/11
Error Code: ORCOMMN-12005
License Server: Displayed as ""

I have already tried the following troubleshooting steps:

Reinstalled PSpice for TI
Restarted the system
Launched the application as Administrator
Verified that the installation completed successfully

Despite these steps, the software is still unable to launch due to the license-related error.

Could you please advise on:

How to restore or reconfigure the PSpice for TI license?
Whether there are any additional license activation steps required after installation?
Any recommended procedure to resolve ORCOMMN-12005?

I would appreciate your guidance on resolving this issue.

LM5169-BUCK-FLY-BUCK-DESIGN-CALC: LM5155-Q1 LTspice Simulation Issue: SS Pin Held Low and No Gate Pulses in 38V to 12V Isolated Flyback

kunal chaturshal — Tue, 02 Jun 2026 13:27:05 GMT

Part Number: LM5169-BUCK-FLY-BUCK-DESIGN-CALC
Other Parts Discussed in Thread: LM5155-Q1, LM5155, LM5169, LM5156

Dear TI Design Support Team,

I am working on an isolated flyback converter design using the LM5155-Q1 controller.

The design specifications are:

Input voltage: 38 V DC
Output voltage: 12 V isolated
Output current: 1 A
Topology: Isolated flyback
Controller: LM5155-Q1
Simulation tool: LTspice 26.0.1
Model used: LM5155_Q1_TRANS.LIB

I am facing an issue where the LM5155-Q1 is not generating any gate pulses. I have checked the important startup pins, and most of the required startup conditions appear to be satisfied. However, the SS pin remains almost at ground level, and the GATE output stays off.

The measured simulation waveforms are approximately:

VBIAS = 38 V
VCC = 6.86 V
UVLO_SYNC = 4.216 V
RT = 0.5 V approximately
COMP = 2.6 V approximately
CS = 0 V approximately
SS = 1 to 2 mV when the external PNP transistor is removed
GATE = 13 mV approximately, with no switching pulses

As per the datasheet, once BIAS, VCC, UVLO, and RT conditions are valid, the SS pin should be charged by the internal soft-start current source. However, in my simulation, the SS pin stays near ground and does not ramp. Because of this, the GATE pin never starts switching.

The current external startup component values are:

RT resistor = 105 kohm from RT to AGND
SS capacitor = 47 nF from SS to AGND
UVLO divider = 909 kohm top resistor and 100 kohm bottom resistor from the 38 V input
VCC capacitor = 2.2 uF
Current sense resistor = 30 milliohm
CS filter = 100 ohm and 470 pF
FB pin is connected to AGND for isolated feedback operation
COMP is pulled up to VCC through 4.99 kohm

I also observed the following behavior related to the SS pin.

When I connect the external PNP transistor together with the optocoupler feedback circuit around the COMP and SS area, the SS pin voltage rises to approximately 2 V. However, when I remove this PNP transistor and keep only the normal SS capacitor connected from SS to AGND, the SS voltage falls back close to 0 V, around 1 to 2 mV.

Additionally, the measured SS pin current remains only in the nA range instead of the expected internal soft-start charging current. This makes me suspect that the SS pin is not being released by the internal soft-start circuit in the model. The earlier 2 V observed on the SS pin may have been caused externally by the PNP and optocoupler feedback network rather than by the LM5155-Q1 internal SS current source.

The key issue can be summarized as follows.

With PNP transistor and optocoupler connected, VSS is approximately 2 V, but there are still no valid gate pulses.

With PNP transistor removed, VSS is approximately 0 V or 1 to 2 mV, SS current remains in the nA range, and GATE remains off.

I would like to request your guidance on the following points:

In the LM5155_Q1_TRANS or LM5155_Q1_TRANS_UNIQUE LTspice/PSpice model, what does the model parameter SS=0 mean? Does SS=0 disable the internal soft-start current source or force the SS pin low?
Should this parameter be removed or changed to SS=1 for normal external soft-start capacitor operation?
Is the pin order and symbol mapping correct for the following subcircuit call?

AGND BIAS COMP CS EP FB GATE PGND PGOOD RT SS UVLO_SYNC VCC

Since VCC, UVLO, RT, COMP, and CS all look valid, what internal condition could still hold the SS pin low and prevent gate switching?
Is there any special startup requirement for simulating the LM5155-Q1 transient model in LTspice, such as using a ramped input source, UIC, startup, or initial conditions?
Could the external PNP transistor and optocoupler feedback network be unintentionally forcing the SS pin to around 2 V, while the internal LM5155-Q1 soft-start circuit is actually not active?
Can you please provide a verified working LTspice or PSpice reference schematic for an isolated flyback converter using LM5155-Q1, or confirm the correct model parameters required for startup simulation?

I have attached the schematic screenshot, waveform screenshot, and full LTspice netlist for your reference.

Thank you for your support. I would appreciate your guidance, as I am currently unable to get the LM5155-Q1 model to release the SS pin and generate gate pulses, even though the external startup pin voltages appear to be valid.

Best regards,
Kunal

with the pnp Bjt Transistor.

without pnp bjt Transistor.

PMP23377: PMP23377 High power Compatibility

Kalyani Raut — Tue, 02 Jun 2026 06:12:29 GMT

Part Number: PMP23377
Other Parts Discussed in Thread: LM5177

Hello,

I am designing a high-power DC-DC bi-directional buck-boost converter with the following specifications:

Input voltage range of 51V to 58V, (Battery Voltage)

Output voltage range of 48V to 54V, (DC bus voltage)
Output power of 2.5kW.

I am evaluating the PMP23377 reference design for a Battery Backup Unit (BBU) application and considering a 2-phase interleaved implementation to achieve approximately 2.5 kW power capability.

I have the following questions:

The PMP23377 is intended for BBU applications and is based on the LM5177 four-switch buck-boost controller. For my application, bidirectional power flow is required:

- Battery charging operation (buck mode)
- Battery discharging operation (boost/buck-boost mode)

Can the PMP23377 architecture be used for both charging and discharging operation without major modifications? If not, what schematic or control changes would be required to support full bidirectional operation?
I would prefer to use an analog controller that also provides an I²C interface for configuration, monitoring, or telemetry.

- Can you suggest any suitable controllers with these features?
- Would such a controller be compatible with the PMP23377 power stage architecture?

IWR6843AOP: Request for Latest .a3dcomp File for IWR6843AOP Radar

Rupal Sharma — Mon, 01 Jun 2026 11:14:24 GMT

Part Number: IWR6843AOP

Hi,

During RF simulation activities, we observed approximately a 0.5 mm positional shift between the STEP model ( IWR6843AOP) taken from TI’s EVM PCB and the encrypted radar simulation model provided by TI, when placing both on the PCB surface for the IWR6843AOP simulation activities.

Could you please help to clarify whether this shift is intentional due to any specific modeling or simulation consideration?

Attached images show the comparison between the encrypted antenna model and the STEP model for reference.

Further to our earlier query, we have a few additional questions regarding the IWR6843AOP model for simulation.

Please help to clarify the queries mentioned in the attached PPT.

Please refer to the attached PPT for details.Radar_Model_Distance.pptx

TPS2HC08-Q1: Footprint and Model are inconsistent

Paul Hamilton — Mon, 01 Jun 2026 06:02:01 GMT

Part Number: TPS2HC08-Q1

Hi All, The footprint and the 3D Model for the TPS2HC08-Q1 appear to be inconsistent and the Model appears to be correct. Has anyone else found that?

PSPICE-FOR-TI: I replaced my PC, and when I install the PSPICE-FOR-TI tool, there's an error says: You have reached the concurrent device access limit.

Veda Leo — Mon, 01 Jun 2026 01:27:28 GMT

Part Number: PSPICE-FOR-TI

You have reached the concurrent device access limit. Too many devices are attempting to connect with the same access key.

UCC28019-DESIGN-CALC: Request for LTspice-Compatible UCC28950 Simulation Model

Supriya K S — Sat, 30 May 2026 09:52:01 GMT

Part Number: UCC28019-DESIGN-CALC
Other Parts Discussed in Thread: UCC28950

Dear TI Support Team,

I am currently working on a power converter design using the UCC28950 phase-shifted full-bridge controller and would like to perform system-level simulations in LTspice.

I downloaded the transient simulation model available for the UCC28950 from the TI website; however, the provided model appears to be an encrypted PSpice model. When attempting to use it in LTspice, the simulation fails due to compatibility and encryption-related issues.

I understand that the existing model is intended for PSpice for TI and that LTspice may not support encrypted PSpice models. However, my complete converter design has already been developed in LTspice, and migrating the entire project to another simulator would be extremely time-consuming.

Therefore, I would like to request one of the following, if available:

An LTspice-compatible simulation model for UCC28950.
An unencrypted PSpice transient model that can be imported into LTspice.
Access to such a model under NDA, if required.
Any recommended procedure or alternative model that can be used for LTspice-based simulation of the UCC28950.

My application involves a Dual Active Bridge (DAB) DC-DC converter, and accurate controller simulation within LTspice is essential for validating the overall system behavior.

I would greatly appreciate your guidance and support regarding the availability of an LTspice-compatible model or any possible workaround.

Thank you for your time and assistance.

Best regards,

Supriya K S
Velankani Information Systems Pvt. Ltd.
supriya.ks@velankanigroup.com

LMR51635-CALC: Unencrypted SPICE file for LMR51636XDDCR

Michael Wall — Fri, 29 May 2026 19:29:46 GMT

Part Number: LMR51635-CALC

Hello, I would like to have access to the unencrypted SPICE file for the LMR51636XDDCR. I saw that I can recieve one if I sign an NDA. Let me know where I can do that.

Thanks!

TPS6289X-Q1-DESIGN: Webench Power Designer - for TPS62442RQRR

Kua Cha — Fri, 29 May 2026 12:46:33 GMT

Part Number: TPS6289X-Q1-DESIGN

TI Support Team

I need to use your Webench Power Designer to simulate the TPS62442RQRR, so that I can get all the components values. However, the Webench says, "Hmm we found TPS62442 but it is not supported in this tool." Could you help to resolve this issue.

Thank you.

UCC28C43-Q1: TIDA-01505 startup issue with optocoupler version

Vincenzo Pio De Marco — Fri, 29 May 2026 09:58:57 GMT

Part Number: UCC28C43-Q1
Other Parts Discussed in Thread: TIDA-01505, , UCC28C43

Hello,

we are debugging a board based on the TIDA-01505 reference design, using only the flyback with optocoupler version.

The converter is expected to start from low input voltage, around 40 VDC, as described in the TIDA-01505 design guide. The UCC28C43-Q1 should start when VDD exceeds the UVLO threshold, around 8.4 V.

At the moment we observe the following behavior.

With the original configuration, applying VIN_HV = 40–60 VDC, the voltage on C54 / UCC28C43 VDD does not rise correctly. It remains around 1.8–2.7 V, so the controller does not start.

We verified that the UCC28C43-Q1 itself is functional:

by externally supplying C54/VDD with 10 V, the controller starts correctly;
VREF = 5 V is present;
COMP ≈ 6.3 V;
CS = 0 V;
OUT pin switches correctly

Therefore, the UCC28C43 and its oscillator/control section appear to be working.

We then checked the HV startup circuit:

Q9 was checked and appears correctly mounted and functional;
Q11 does not appear to be forcing Q9 off;
removing D35 did not change the issue;
the HV startup resistor chain is not open. For example, with VIN_HV = 60 V we measured approximately:
- high side of R48: 21.5 V
- low side of R48 / high side of R49: 11.4–11.5 V
- low side of R49: 3 V
- Q9 pins around 3 V / 2.6 V / 1.85 V
- C54 around 1.85 V

The important observation is related to the level-shifter branch:

If R59 is removed, C54/VDD rises to approximately 10 V with VIN_HV = 60 V.
If Q19 is removed and R87 is changed to 10 kohm,
C54/VDD can rise to about 9 V even from VIN_HV = 40 V.
However, when Q19 is mounted, C54/VDD collapses again to approximately 2.7 V.
Q19 was replaced with a new component, but the behavior did not change.
Removing R96 allows C54/VDD to rise to about 9 V, but without R96 the SiC gate is no longer driven, so R96 appears necessary for Q19 / level-shifter operation.
Changing R96 to 10 kohm still causes Q19 to become polarized and the startup remains blocked.
R87 was also tested as a stronger pull-up, for example 3 kohm, but the issue remained.
Measured VGS of Q19 is around −0.75 V in the problematic condition

So the current conclusion is that the Q19/R96/R87/R59 level-shifter branch loads or clamps the VDD/startup node during startup, preventing C54 from reaching the UCC28C43 UVLO turn-on threshold.

Could you please clarify the intended startup behavior of this branch in the optocoupler version of TIDA-01505?

In particular:

Are R58/R59 intended to be mounted as 0 ohm links in the default optocoupler configuration, or are they only for a specific level-shifter supply option?
Is the level shifter supply expected to be pre-biased through J14 before applying the main HV input?
What are the correct default values / population options for R87, R96, R58, R59, Q19, and the related level-shifter startup components?
Is there any known correction or modification to the TIDA-01505 schematic/BOM for reliable startup from 40 V using the optocoupler version?
Based on the measurements above, which component or population option should be changed to prevent Q19 from pulling down the VDD/startup node during startup?

Thank you.

TPSF12C3QEVM: Availability of TPSF12C1/TPSF12C3

Ryota Morimoto — Fri, 29 May 2026 08:06:34 GMT

Part Number: TPSF12C3QEVM
Other Parts Discussed in Thread: TPSF12C1, TPSF12C3

Hello,

we cannot see Active EMI filters (TPSF12C1/TPSF12C3) datasheet. Are these components not continued?

Is there any other similar the active EMI filters?

Thanks.

Ryota

LMR36015: Design Verification of LMR36015ARNXR PCB layout sorrounding area

Souradeep Pal — Fri, 29 May 2026 08:00:41 GMT

Part Number: LMR36015

Hello,
Everyone,
I used LMR36015ARNXR for 48V to 12V conversion. I simulated (WEbench) based on the output current rating and find out 0.7watt loss in the IC.
Kindly find my circuit and pcb layout area of this IC. Is the design okay?

PSPICE-FOR-TI: PSPICE-FOR-TI: Concurrent device limit reached

jgorsk — Fri, 29 May 2026 07:27:50 GMT

Part Number: PSPICE-FOR-TI

Hello,

Can you reset the record for all my PCs so I can install TI PSPICE on a new PC please?