Simulation, hardware & system design tools forum - Recent Threads

MSPM0-SDK: Access denied to download

Eduardo Rodriguez — Thu, 02 Jul 2026 20:46:39 GMT

Part Number: MSPM0-SDK

I am writing because my request to download a TI software package has been denied. When I attempt to download it, I receive the following message:

"Access denied. We are unable to approve your download at this time."

I believe this may be an error, as I require access to this software for academic/research purposes. I kindly request that you review my account and let me know if any additional information or verification is needed to restore my download access.

Thank you for your time and assistance. I look forward to your response.

RE: TPS6521905-NVM-XILINX-1: Request for SPICE Models for TPS6521905WRHBRQ1, TPS62810MWRWYR, TPS546D24ARVFR, and TPS51200DRCR

Sarah Lao — Thu, 02 Jul 2026 20:01:04 GMT

Hi Mohd,

I can only speak on the two PMIC devices in your list,
please create separate threads for TPS62810MWRWYR and TPS546D24ARVFR if you need specific help for these parts.

Generally, any models we have will be available under the "Design & development > Design tools & simulation: section of the product page.

For TPS51200, we have the following models available on the product page:

For TPS65219, we do not have any SPICE models available but we do have a SIMPLIS model available: https://www.ti.com/lit/zip/slvmeh6

It looks like the other two devices in your list also have models available on their respective product pages.
Let me know if you need any more help here, thanks!

Best Regards,
Sarah

TPS6521905-NVM-XILINX-1: Request for SPICE Models for TPS6521905WRHBRQ1, TPS62810MWRWYR, TPS546D24ARVFR, and TPS51200DRCR

mohd hamza anwar — Thu, 02 Jul 2026 11:34:06 GMT

Part Number: TPS6521905-NVM-XILINX-1

Hi everyone,

I want to simulate the following power converters, but I'm unable to find SPICE/PSpice models for them:

TPS6521905WRHBRQ1
TPS62810MWRWYR
TPS546D24ARVFR
TPS51200DRCR

Has anyone worked with these devices before? Are SPICE models available somewhere, or is there another recommended way to simulate them? Any equivalent models or suggestions would be really helpful.

Thanks!

RE: LM5149-LM25149DESIGN-CALC: Having issues with simulating LM5149 in OrCAD CAPTURE CIS

Timothy Hegarty — Thu, 02 Jul 2026 17:13:31 GMT

No problem, thanks Jayant.

LM5149-LM25149DESIGN-CALC: Having issues with simulating LM5149 in OrCAD CAPTURE CIS

Jayant Yadav — Thu, 25 Jun 2026 17:45:24 GMT

Part Number: LM5149-LM25149DESIGN-CALC

Part Number: LM5149-Q1
Simulation Tool: OrCAD PSpice (Version 25.1.0)
Design Files: Official TI PSpice Transient Model (snvmcb8)

Title:
LM5149-Q1 PSpice Simulation Error: ORPSIM-15141 Less than 2 connections at CNFG pin node.

Description:
I am trying to run a transient simulation of the LM5149-Q1 using the official PSpice transient model downloaded directly from the TI product page. My goal is to analyze the power stage output voltage waveforms and overall loop stability.

However, the PSpice netlist generator fails to compile, throwing an ORPSIM-15141 error pointing directly to the CNFG pin (Pin 5) configuration node.

Error Log Details:

X_U2 0 N07529 0 N06736 N07786 N05878 N053186 N053187 N06813 N06153 + N07052 N06845 0 N07040 N08313 N07790 N06160 N06746 N06643 N07070 N06488 N05878 + N07070 0 0 LM5149-Q1_TRANS PARAMS: STEADY_STATE=0

R_R8 0 N07786 24.9k TC=0,0

ERROR(ORPSIM-15141): Less than 2 connections at node N07786.

Troubleshooting Already Attempted:

Verified physical schematic routing multiple times. Resistor R8 (24.9k) is visibly wired between the CNFG pin and Ground.
Replaced the resistor component and placed a fresh instance on the schematic to eliminate any hidden connection glitches.
Attempted to isolate the pin by connecting a 1-Gigaohm dummy load resistor to ground. The simulation still threw the identical "Less than 2 connections" error at the CNFG node.
Exported the .lib file directly to a new Capture Part Library via the PSpice Model Editor to generate a fresh .olb symbol, but the pin-mismatch compilation crash persists.
In the OLB graphic library property editor, the CNFG pin type is natively designated as "Bidirectional".

Full error code of the latest run:


**** 06/25/26 22:02:01 ***** PSpice 25.1.0 (25 March 2026) **** ID# 0 ********

 ** Profile: "SCHEMATIC1-LM_5149"  [ c:\users\idk\documents\kaza baseboard\simulations\lm_5148\lm_514-PSpiceFiles\SCHEMATIC1\LM_5149.


 ****     CIRCUIT DESCRIPTION


******************************************************************************




** Creating circuit file "LM_5149.cir" 
** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS

*Libraries: 
* Profile Libraries :
* Local Libraries :
.LIB "C:/Users/idk/Downloads/slpm041b/CSD18503Q5A.lib" 
.LIB "C:/Users/idk/Downloads/snvmcb8/lm5149-q1_trans.lib" 
* From [PSPICE NETLIST] section of C:\SPB_Data\cdssetup\OrCAD_PSpice\25.1.0\PSpice.ini file:
.lib "nom.lib" 

*Analysis directives: 
.TRAN  0 10ms 0 0.1ms 
.OPTIONS ADVCONV
.PROBE64 V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*)) 
.INC "..\SCHEMATIC1.net" 



**** INCLUDING SCHEMATIC1.net ****
* source LM_514
X_U2         0 N07529 0 N06736 N07786 N05878 N053186 N053187 N06813 N06153
+  N07052 N06845 0 N07040 N08313 N07790 N06160 N06746 N06643 N07070 N06488 N05878
+  N07070 0 0 LM5149-Q1_TRANS PARAMS:  STEADY_STATE=0
V_V1         N05874 0 0Vdc
L_L1         N05874 N05878  0.68u  TC=0,0 
C_C1         0 N05887  0.1u  TC=0,0 
C_C2         0 N05878  47u  TC=0,0 
R_R1         N05887 N05874  0.47 TC=0,0 
C_C3         N06160 N05874  0.1u  TC=0,0 
C_C4         N06136 N05874  0.47u  TC=0,0 
R_R2         N06153 N06136  3 TC=0,0 
R_R3         N06228 N06153  200 TC=0,0 
C_C5         N06160 N06228  1n  TC=0,0 
R_R4         N06160 N06153  49.9k TC=0,0 
C_C6         0 N06488  0.1u  TC=0,0 
R_R5         N06488 N053187  49.9k TC=0,0 
C_C7         0 N06643  1n  TC=0,0 
C_C8         N06746 N06736  0.1u  TC=0,0 
X_X1         N05878 N06813 N06746 csd18503q5a PARAMS:
X_X2         N06746 N06845 N07040 csd18503q5a PARAMS:
L_L2         N06746 N07052  0.68u  TC=0,0 
R_R6         N07052 N07070  8m TC=0,0 
C_C9         0 N05878  10p  TC=0,0 
C_C10         0 N05878  10p  TC=0,0 
C_C11         0 N07070  47u  TC=0,0 
C_C12         0 N07070  47u  TC=0,0 
C_C13         0 N07070  47u  TC=0,0 
C_C14         0 N07070  47u  TC=0,0 
R_R7         N06643 N07529  3 TC=0,0 
C_C15         0 N07529  2.2u  TC=0,0 
R_R8         0 N07786  24.9k TC=0,0 
R_R9         0 N07790  9.52k TC=0,0 
R_R10         N06488 N08313  100k TC=0,0 
R_R11         N084131 N053186  24.3k TC=0,0 
C_C16         0 N084131  1.1n  TC=0,0 


** Wrapper definitions for AA legacy support **

.subckt csd18503q5a  1 2 3

.param  ptrc1    7.00e-3  
.param  ptrc2    2.0e-5
.param  pwidthp  4.02
.param  pwidth   {pwidthp*1e6}
.param  perimp   {2.1*pwidthp}
.param  perim    {perimp*1e6}
m1   10 11 12 12  nmos  w={pwidthp} l=0.5u  ps={perimp} pd={perimp}
xcgd    5       10      1       3       cgd
cgs     5       8       1.04e-9
xcds    8       10      1       3       cds
dbd     3       1       dbd {4.02/5.788666666666666666666666666666666666666666666667}
lgg   2  5       2.1e-9
rgg   5 11       4.40
rsb  12  9       rtemp 0.23166e-3
r   9  8         rtemp 0.23166e-3
rsp   8  6       0.55e-3
l   6  3         0.47e-9
rsl   6  3   0.5
rdd   7 10       rtemp 2.05e-3
rdp   4  7       0.5e-4
ldd   1  4       0.05e-9

.model nmos nmos
+ level=7
+ version=3.2
+ capmod=2
+ nlx=1.74e-07
+ vbm=-5
+ dvt0=2.2
+ dvt1=0.53
+ dvt2=-0.032
+ u0=650
+ ua=1.4e-09
+ ub=5e-18
+ a0=1
+ ags=0
+ a1=0
+ a2=1
+ lint=5.5e-08
+ voff=-0.28
+ nfactor=2
+ eta0=0.005
+ etab=-0.07
+ dsub=1.4
+ pclm=0.25
+ pdiblc1=0.02
+ pdiblc2=0.004
+ drout=0.9
+ pscbe1=3e+08
+ pscbe2=1e-06
+ pvag=0.1
+ delta=0.022
+ js=0
+ cgso=1e-18
+ cgdo=1e-18
+ cgbo=1e-18
+ cj=1e-18
+ cjsw=1e-18
+ cf=0
+ tnom=25
+ ute=-1.5
+ kt1=-0.85
+ kt1l=1e-15
+ kt2=0.022
+ ua1=2.5e-11
+ ub1=-8e-19
+ tox=4e-08
+ xj=3e-07
+ nch=1.275e+17
+ nsub=1e+16


.model pmosd pmos
+ level=1
+ tnom=27
+ vto=-0.3
+ is=6e-14
+ tox=4e-08
+ nsub=1.5e+18
+ gamma=10
+ cj=1e-18
+ cjsw=1e-18
+ cgso=1e-18
+ cgdo=1e-18
+ cgbo=0


.model dbd d
+ cjo=7.5e-15
+ vj=0.5
+ m=0.625
+ tnom=25
+ fc=0.5
+ tt=2e-09
+ xti=3.3
+ bv=41
+ is=7e-12
+ n=1.045
+ rs=0.000625
+ trs1=0.004


.model rtemp res


.model ddx d
+ cjo=8.5e-11
+ vj=0.5
+ m=0.45
+ is=1e-12
+ rs=1
+ tnom=27

.ends csd18503q5a


**** RESUMING LM_5149.cir ****
.END

ERROR(ORPSIM-15141): Less than 2 connections at node N07786.

RE: LM5149-LM25149DESIGN-CALC: Having issues with simulating LM5149 in OrCAD CAPTURE CIS

Jayant Yadav — Thu, 02 Jul 2026 16:53:48 GMT

Thank you for the file, i will update on the same.

RE: UC1843A-EP: ESD class and SPICE model for UC1843AMDREP

John Gomez — Thu, 02 Jul 2026 16:48:45 GMT

Hi Adam,

Could you please clarify why that assumption would be made?

UC1843A-EP: ESD class and SPICE model for UC1843AMDREP

Adam Shiau — Thu, 25 Jun 2026 08:54:45 GMT

Part Number: UC1843A-EP

Hi TI team,

I'm looking into using the UC1843AMDREP and have a couple of quick questions.

I checked the reliability report and noticed it mentions ESD-HBM results, but I couldn't find any specific ESD details in the datasheet itself.

Since this is for a high-reliability design, we just want to make sure if this part happens to be ESD Class 0.

Also, is there a SPICE model available for this specific part number?

Thanks for the help!

Best,

Adam

TPS7H4003-SEP: SIMULATION TRANSIENT MODEL

Ajith Kumar M — Wed, 01 Jul 2026 10:32:40 GMT

Part Number: TPS7H4003-SEP

I AM USING THIS MODULE IN MY SPACE PROJECT. I NEED TO CHECK THE SIMULATION FOR THIS MODULE. WE DONT HAVE PSPICE LICENCESES VERSION SO CAN YOU PLEASE PROVIDE THE LTSPICE OR TINA TI SPICE TRANSIENT MODEL.

RE: TPS7H4003-SEP: SIMULATION TRANSIENT MODEL

Sarah Koch — Thu, 02 Jul 2026 15:33:39 GMT

It is a fully free version. Cadence only places limitations on the simulator (limiting traces in the sim waveform viewer, for example) if multiple non-TI components are imported. There is more information and documentation on the download page if you are interested: https://www.ti.com/tool/PSPICE-FOR-TI

Thanks,

Sarah

RE: DP83TG720-SCHEMATIC-CHECKLIST: 1000base-t1 IBIS-AMI

hiroyuki yajima — Thu, 02 Jul 2026 12:59:33 GMT

I got it.

Thank you so much.

DP83TG720-SCHEMATIC-CHECKLIST: 1000base-t1 IBIS-AMI

hiroyuki yajima — Wed, 01 Jul 2026 05:32:59 GMT

Part Number: DP83TG720-SCHEMATIC-CHECKLIST

I would like to obtain the IBIS-AMI model to verify 1000base-t1 Ethernet connectivity through analysis.
Could you please provide it?

PSPICE-FOR-TI: Question about LM74700‑Q1 PSpice model behavior

Taichi Utsumi — Thu, 02 Jul 2026 11:40:00 GMT

Part Number: PSPICE-FOR-TI

Hello,

I am simulating the LM74700‑Q1 ideal diode controller using the official PSpice for TI model. However, the device does not behave as expected, and I would like to confirm whether the model is functioning correctly.

In my simulation:

VCAP stays at the same voltage as ANODE (24 V)
V(GATE) − V(ANODE) is only about 80 µV
The gate never rises above the ANODE voltage
Even when EN is pulled low, the gate voltage still follows the supply ramp

Because of this, the MOSFET only conducts through its body diode, and the ideal‑diode behavior (gate boosting above ANODE) never occurs.

I have checked the pin mapping and connections, and the circuit itself does not operate even before considering pin‑number mismatches.

My question: Is the LM74700‑Q1 PSpice model intended to simulate the internal charge pump and ideal‑diode behavior? Or is the model simplified and does not include gate boosting above ANODE?

Any clarification about the expected behavior of this model would be greatly appreciated.

Thank you.

RE: DP83TG720-SCHEMATIC-CHECKLIST: 1000base-t1 IBIS-AMI

hiroyuki yajima — Thu, 02 Jul 2026 10:49:09 GMT

Thank you for the advice.
I have checked this IBIS model.
How do I configure it for 1000BASE-T1 PAM3?
Since it is not an IBIS-AMI model, I assume PAM3 analysis is not possible.

RE: TPS7H4003-SEP: SIMULATION TRANSIENT MODEL

Ajith Kumar M — Thu, 02 Jul 2026 10:07:54 GMT

Thank you for your support. Is that P-spice for TI is trial version or payable version. If it is not a paid version, how many days can i use this P-spice tool?

LM706A0-Q1: The Pspice model .lib file is encrypted

Sakshi Anwekar — Thu, 02 Jul 2026 09:05:37 GMT

Part Number: LM706A0-Q1

The Pspice model .lib file is encrypted requesting for the unencrypted .lib file

LM706A0-Q1: issue with spice model

Sakshi Anwekar — Thu, 02 Jul 2026 08:56:41 GMT

Part Number: LM706A0-Q1

Issue with LM706A0QRRXRQ1 Pspice model .lib file

LMR51635: Request for Documentation (Shizuoka) LMR51635

NIRASAWA YUI — Wed, 01 Jul 2026 08:45:28 GMT

Part Number: LMR51635

Dear Sir/Madam,

Thank you for your continued support.

I would like to kindly ask for your guidance regarding the LMR51635 on the following two points:

1. Thermal resistance on a 2-layer PCB
If you have any documents, graphs, or other reference materials showing the relationship between copper area and thermal resistance on a 2-layer PCB, I would greatly appreciate it if you could share them with us.

2. Thermal resistance differences due to product variants
I understand that the LMR51635 series includes multiple variants. Could you please confirm whether there is any difference in thermal resistance depending on the specification or variant? If there are any differences, I would appreciate it if you could also let us know the details.

Thank you very much for your assistance.

RE: LMR51635: Request for Documentation (Shizuoka) LMR51635

Sourish Nandy — Thu, 02 Jul 2026 08:50:05 GMT

Hello Nirasawa,

Here are the answers for your questions]

1) We do not have any such document specifically for the LMR51635. But we do have such a characterization in datasheet of LM43603 as shown below:

Here is one more document where the same plot is provided: Thermal Design made SIMPLE with LM43603 and LM46002

The trend will be similar in the LMR51635 device too.

Here is another document explaining the thermal design: AN-2020 Thermal Design By Insight, Not Hindsight (Rev. C)

You can use other publicly available tools on the internet for helping you in PCB design.

One such example is: Simplify PCB Design with Our Trace Width Calculator | AdvancedPCB

2) The different variant of LMR51635 series would have same thermal resistance equal to the value provided in datasheet.

Regards,

Sourish

RE: TPSM861253EVM: un-encrypted spice file for TPSM861253RDXR

Alla Ushasri — Thu, 02 Jul 2026 07:55:22 GMT

Hi Joel,

We don't have Unencrypted Pspice circuit level model, it is directly converted from SIMPLIS!

Regards,

Usha.

TPSM861253EVM: un-encrypted spice file for TPSM861253RDXR

Joel Edmund — Thu, 25 Jun 2026 22:45:07 GMT

Part Number: TPSM861253EVM

Hello, to whom this reach.

I'm here on a request, for some time now i have been study the LM5118 data sheet and now finally generated a working schematic from a new project on PSpice for TI. On almost completion i received an email from a News Letter from Murata stating they have a new sensor which detects vibration for faulty ball bearing or electrical motor. For me to intergrage this to the newly generated schametic i need to lower my 12 Vout to 3v - 5v, this is how i came across the TPSM861253RDXR ic.

On me using the un-encrypted version of the LM5118 with no alteration, i will love to do the same with the TPSM861253RDXR.

Opening up the TPSM861253 PSpice file i notice the spice file where encrypted.

If possible, is there anyway i can get the un-encrypted spice file for the TPSM861253RDXR ic?

thanks so much,

joel.

LM5067QUICK-CALC: i am facing LM5060 simulations error

Aparajita Dash — Fri, 26 Jun 2026 09:39:16 GMT

Part Number: LM5067QUICK-CALC

Hello,

I am simulating the LM5060 in LTspice . Trying get boost voltage by following application circuit and input is 48V,However, I am getting the following error:

My goal is to implement a gate driver that outputs or boost more than input supply ( more than 50 and less than 65V)

Error:

Questionable use of curly braces in "b§e_abmgate yint 0 v={if(v(a)>{{vthresh}},{{vss}},{{vdd}})}"
Error: undefined symbol in: "if([v](a)>((vthresh)),((vss)),((vdd)))"

RE: LM5067QUICK-CALC: i am facing LM5060 simulations error

Aparajita Dash — Thu, 02 Jul 2026 06:46:21 GMT

Could you please suggest any NFET high side Driver with charge pump which has spice model . Thank you in advance.

DP83TG720-SCHEMATIC-CHECKLIST: Requesting SGMII time domain and frequency domain simulation (Eye mask and IL and RL mask) for signal integrity validation

Monish S — Thu, 02 Jul 2026 05:39:45 GMT

Part Number: DP83TG720-SCHEMATIC-CHECKLIST

As we are doing Signal integrity analysis for SGMII, We required specifacation limits details such as (Eye mask, Insertion loss, Return loss, Crosstalk) for validating the design preformance for SGMII interface, sharing for RGMII also is added advantage.

I have seen the eye mask spec for DP83TG720S-QI datasheet, is it for PHY to Connector section or FPGA to PHY section? or we can use same mask for both side, Kindly clarify

RE: LM5067QUICK-CALC: i am facing LM5060 simulations error

Aparajita Dash — Thu, 02 Jul 2026 04:55:45 GMT

Hi Avisek,

Can i get the reply for above query