https://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/Jump start system design and speed time to market with comprehensive designs including schematics or block diagrams, BOMs, design files and test reports. Connect here to the experts with deep system and product knowledgeen-USTelligent Community 13https://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1642088/uc1843-sp-uc1843bevm-cval/6338148Fri, 08 May 2026 14:07:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:70af2526-8a46-4451-bd7b-b51375860a1dDaniel HartungHey Jan, I am reminded of another design that might be worth checking out: https://www.ti.com/tool/PMP23033 Thanks, Danielhttps://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1642718/ucd3138128-ucd3138128pfc-programming-issue/6337962Fri, 08 May 2026 11:19:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:b3bd92bf-770b-49ca-a1d7-d4e5092b27a7Bishal MondalHi Getvara, Yes, you can use UCD3138A64OEVM-662 for reading and reprograming UCD3138128PFC. Thanks, and Regards Bishal Mondalhttps://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1643853/pspice-for-ti-more-detailed-training-material-and-importing-altium-designsFri, 08 May 2026 09:28:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2a9a56b9-24a4-4f27-a623-64405c973a71franziskusPart Number: PSPICE-FOR-TI Team, where do we have more detailed training material to share with customers? Are there instructions for how to import Altium designs? Best regardsPSPICE-FOR-TIhttps://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1640442/lm5156-q1-external-circuit-design/6337744Fri, 08 May 2026 08:04:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:80e62da7-852d-499a-a5ca-ea5320ce5a10Niklas SchwarzHi Zhexi, This type of operation is a normal working condition. The IC is not broken. Therefore I asked what kind of problem this operation mode is causing on customer side. Best regards, Niklashttps://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1640442/lm5156-q1-external-circuit-design/6337729Fri, 08 May 2026 07:55:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c5b8ac1e-2737-4b4d-8e05-2b68b966017ezhexi zhangHi Niklas, Thank you for your instant reply. Does it mean the chip is broken or it is just working condition problem? Best regards, zhexihttps://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1640442/lm5156-q1-external-circuit-design/6337685Fri, 08 May 2026 07:21:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:382f7d0a-e46d-4327-8e54-9cd4b222999cNiklas SchwarzHi Zhexi, The are multiple possibilities for a gate driver signal like this. In light load condition, the duty cycle can become very small down to minimum on-time of the device. On the other side, if the load is too large, the device may trigger cycle-by-cycle overcurrent protection and the duty cycle gets limited because of this. Can you give additional background for this question? Is the output voltage not regulated properly, or is there another problem why this waveform causes problems? Thanks and best regards, Niklashttps://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1640442/lm5156-q1-external-circuit-design/6337419Fri, 08 May 2026 04:04:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:4a7ed866-8900-42ee-a2fd-9f1dacf036d6zhexi zhangAnd in what situation, the gate pin will generate this waveform.https://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1643651/tms320f28069-sanitization-procedure/6337200Thu, 07 May 2026 23:26:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:dd206978-8524-4c24-803c-35701bdf683bMatthewPateDavid, Statement of volatility attached, gives process to sanitize the memories on this device. e2e.ti.com/.../Statement-of-Volatility_5F00_TMS320F28069_5F00_68_5F00_67.pdf Best, Matthewhttps://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1643564/am6421-am6421-gpmc-multi-cs-configuration-capacitive-loading/6337131Thu, 07 May 2026 21:55:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:b2644478-f0dd-4705-ba60-3d27a28f0591Mark MHi Harshith, Good questions. [quote userid="696597" url="~/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1643564/am6421-am6421-gpmc-multi-cs-configuration-capacitive-loading"]Q1 — PCB Layout Recommendations for Shared GPMC Bus[/quote] Except for the 16-bit 133MHz synchronous mode, we actually ran timings analysis for GPMC from 3pF to 30pF (the datasheet reads 5 to 20pF of loading. You might want to try simulating the design first to evaluate the stub reflections and experiment with placement of signal branching. TI IBIS files and Infineon IBIS files are availble. You may be able to get IBIS from MicroChip for the IGLOO FPGA. GPMC has separate timings for each chip select. You may need to slow down the on all chip selects to give time for the signals to settle and have robust timings. If you know one endpoint is going to run with faster rates than the other, then you may try to route fly-by from with the slower memory in the middle. That might let you achieve better timings for the faster memory. Adding buffers may be an option to consider. [quote userid="696597" url="~/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1643564/am6421-am6421-gpmc-multi-cs-configuration-capacitive-loading"]Q2 — Recommended Bring-Up Sequence for Multi-CS Validation[/quote] All 4 GPMC Chip selects are routed to the AM64x EVM (TMDS64EVM/ PROC101) HIGH SPEED EXPANSION CONNECTOR (SEAF-30-06.0-L-05-2-A-K-TR) https://www.ti.com/tool/TMDS64EVM AM64 IO LINK/BREAKOUT BOARD The GPMC address bus for IOSET2 is routable to the headers Use Datasheet Table 6-64. GPMC0 IOSETs https://www.ti.com/tool/TMDS64DC01EVM Schematics for that board /cfs-file/__key/communityserver-discussions-components-files/234/PROC102E1_5F00_SCH.pdf Since GPMC is so configurable with per-chip-select timings, I recommend starting with very relaxed timings for all chip selects. Then increase speed incrementally while performing write read verify operations across voltage and temperature ranges if you can. You might try building some boards with one of the GPMC endpoints removed to evaluate the impact on loading. I am aware of no in-built loopback tests. Write read verify from the memory is the loopback test. I'm willing to work with you to get this working. Regards, Markhttps://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1642773/pspice-for-ti-can-t-install-pspice-for-ti/6337009Thu, 07 May 2026 20:05:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:565e90f6-7d8b-4456-a972-98e31548d0efBob Aivatii figured it out you cannot copy and paste the access code- you need to type in all the characters - amazing no one in the expert team knew this! disappointing after 2 days no one repliedhttps://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1643651/tms320f28069-sanitization-procedureThu, 07 May 2026 19:57:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:0d78a355-16fb-46ab-88ca-a369c50a3869David GonsalezPart Number: TMS320F28069 I am looking for a Sanitization procedure, I need to ensure all memory is wiped from this device.TMS320F28069Aerospace & Defensehttps://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1643564/am6421-am6421-gpmc-multi-cs-configuration-capacitive-loadingThu, 07 May 2026 14:46:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:bcc2b01c-55d8-4c56-91d2-b00c4def1f9aHarshith SBPart Number: AM6421 Other Parts Discussed in Thread: TMDS64EVM Hi TI Team, This post is a follow-up to our earlier software query on GPMC multi-CS configuration, where a TI engineer Mr. Anil recommended we raise a separate thread for hardware design guidance: e2e.ti.com/.../6326115 To summarise the problem points from that thread: We have not tested this pattern, and my suggestion is to raise a new e2e for the specific use case of GPMC so that hardware experts can provide proper HW design recommendations. Signal integrity concern remains: Multiple devices sharing GPMC_A[n:0], GPMC_D[15:0], GPMC_OE, GPMC_WE, and GPMC_BE lines increase capacitive loading. Our Hardware Configuration Custom board with the following devices connected to the GPMC bus: 1. FPGA — Microsemi Igloo2 M2GL090-FG676 - CS0 and CS2 - Non-Multiplexed 16-bit NOR Asynchronous - 3.3V I/O 2. NV_SRAM — Cypress CY14B116N-ZSP25XI (1M × 16-bit, 25ns) - CS3 - Non-Multiplexed 16-bit Asynchronous SRAM - 3.3V I/O Shared signals across all three CS lines: - GPMC_A[21:0] — 22 Address lines - GPMC_D[15:0] — 16-bit Data bus - GPMC_OE, GPMC_WE, GPMC_BE0, GPMC_BE1 Hardware Questions: Q1 — PCB Layout Recommendations for Shared GPMC Bus we want to understand what to look for during board bring-up from a signal integrity standpoint: - Are there specific signal groups (e.g., GPMC_OE, GPMC_WE) that are more susceptible to capacitive loading issues and should be prioritised for oscilloscope verification? - What are the acceptable signal rise/fall time limits on GPMC address and data lines in Asynchronous NOR mode? - Are stub lengths to each device a concern in async mode, and if so what is an acceptable stub length? Q2 — Recommended Bring-Up Sequence for Multi-CS Validation Since TI's EVM only validates CS0, we want to establish a safe bring-up sequence to validate CS2 and CS3 independently before enabling all three simultaneously: - Is there a recommended bring-up and validation sequence for a multi-CS GPMC configuration? - Are there any specific GPMC diagnostic registers or loopback test modes on the AM6421 that can assist in isolating per-CS signal integrity issues during bring-up? Thank you for your support. Do let us know what is required from our side to get started on this. Regards, Harshith PhytecIndustrial AutomationAM6421TMDS64DC01EVMTMDS64EVMhttps://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1643150/bq41z90evm-can-t-calibrate-device-batt-gain/6336484Thu, 07 May 2026 14:29:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:38110b35-3d2c-4d0e-a18b-1140fabcc291Alan FriasHello, This question has been assigned within the team and will be reviewed and followed up with another application engineer when possible. In the meantime please attach any associated .log/.gg files associated with the projects. *Responses may be delay due to large amount of question in the e2e queue Thank you, Alanhttps://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1642088/uc1843-sp-uc1843bevm-cval/6336483Thu, 07 May 2026 14:29:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:fd53d81a-a5cb-4e0f-9c16-d203c0c43eefDaniel HartungHey Jan, It is because we highly suggest not using the UC1901-SP in new designs. Thanks, Danielhttps://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1642088/uc1843-sp-uc1843bevm-cval/6336185Thu, 07 May 2026 10:26:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:a97e79bd-f7da-4c02-aab5-f2e02598b0a2Jan R. PetersenHi Daniel I'm sorry to hear that and I find it a little strange that you sell an EVM, where all functions are not supported. Best regards Janhttps://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1642838/tas5806md-should-the-differential-output-traces-of-the-audio-amplifier-be-impedance-controlled/6335903Thu, 07 May 2026 06:54:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ef44ca8c-e599-4105-9898-c60364de89d2Peter Wu5Hi, No, the differential output traces for the TAS5806MD do not need to be designed as controlled impedance lines (such as 90 Ω or 100 Ω differential).You do not need to run complex impedance calculations or ask your PCB manufacturer for exotic "controlled impedance" specs. Simply use wide, continuous copper pour for the outputs and ensure the two traces in each differential pair are perfectly balanced.https://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1642838/tas5806md-should-the-differential-output-traces-of-the-audio-amplifier-be-impedance-controlled/6335733Thu, 07 May 2026 04:33:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:63cf996d-4b07-4360-b3ae-0030cdcbb5f1Mahetab PatelHi Peter, Thank you for your insights. Could you please confirm whether the differential traces need to be designed for a specific impedance, such as 100 Ω or 90 Ω?https://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1643048/lsf0108-lsf0108pwr-tina-or-ltspice-model-request/6335708Thu, 07 May 2026 03:39:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c3c790a3-2468-451b-bff9-6cfce5e09171krish krishHi Jack, Thank you for the model.https://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1642838/tas5806md-should-the-differential-output-traces-of-the-audio-amplifier-be-impedance-controlled/6335631Thu, 07 May 2026 02:18:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f524bc6a-52c6-43c4-be5f-25ce1cd64e38Peter Wu5Hi, Here are additional design tips for your reference. When routing these pins, adhere to the following principles: Trace Width: To balance low resistance and interference immunity, it is recommended that the output trace width meet or exceed 20 mil (approx. 0.5 mm)​ according to standard fabrication capabilities. If your device outputs high power (e.g., >10W into a 4Ω load), it is advisable to increase the width to 40 mil (approx. 1 mm) or 60 mil (approx. 1.5 mm), depending on your expected peak current calculations. Strict Length Matching: This is the most critical requirement​ for differential pair routing. OUT_A+ and OUT_A- must be strictly symmetrical, with length mismatches controlled within a minimal range (typically recommended within ±5 mil). Similarly, OUT_B+ and OUT_B- should also be strictly matched. Under no circumstances should these two differential pairs cross each other, as this would disrupt the differential signal balance and increase common-mode noise. Keep Away from Noise Sources: The output traces of a Class-D amplifier act as high-frequency antennas. During layout, keep trace lengths as short as possible and route them away from sensitive analog signals (such as audio input interfaces, I2S/I2C lines, reference voltage pins, etc.) to prevent high-frequency noise coupling into the audio system, which causes distortion or noise. Reference Plane: Maintain a solid ground plane beneath the differential pairs to provide a stable return path and reduce electromagnetic radiation. Connection to LC Filter: Traces should terminate directly at the external LC filter (typically a ferrite bead or power inductor + ceramic capacitor). Ensure the pads connecting to the inductor are sufficiently large to further reduce connection impedance. Please let me know if you have additional questions. Thanks.https://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1642838/tas5806md-should-the-differential-output-traces-of-the-audio-amplifier-be-impedance-controlled/6335621Thu, 07 May 2026 02:05:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d79f717c-79f9-47f4-b6bb-6c02bee366a3Peter Wu5Hi, The core purpose of using wide traces is not impedance matching, but to reduce DC resistance (DCR), handle high current, and minimize heat generation. Reducing DC Resistance (DCR): The output side of a Class-D amplifier is effectively connected to a power inductor (the output filter inductor). If the output traces are too thin, their parasitic resistance forms additional series impedance with this inductor. This leads to two issues: DC Voltage Drop: When high DC bias current flows, thin traces create significant voltage drops, reducing the actual operating voltage at the speaker terminals and thus decreasing output power. Heat Generation: High current flowing through thin traces generates Joule heating ( P = I 2 R ). This not only wastes energy but can also affect the stability of the chip and inductors (especially in high-temperature environments). Handling Peak Current: Although Class-D amplifiers are highly efficient, they can experience instantaneous high peak currents in the output pins and traces when delivering high power. Wide copper pours provide a low-resistance path to ensure smooth current delivery.