https://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/Jump start system design and speed time to market with comprehensive designs including schematics or block diagrams, BOMs, design files and test reports. Connect here to the experts with deep system and product knowledgeen-USTelligent Community 13https://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1696260/ucc28950-ucc28950-hiccup-mode/6538366Fri, 13 Nov 2026 08:31:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:39f6b8aa-ad63-486e-9860-e5b66a7443b9Govind RaiHi, To answer your question directly: Yes, during a continuous hard short, the controller will stay in a continuous hiccup loop —it will attempt to soft-start, hit the 2 V cycle-by-cycle current limit, shut down once VSS drops below 3.6 V, wait out the off-time, and try again until the short is removed or input power is cycled. It does not permanently latch off by default. Why this is safe for the power stage: Because the discharge current during the off-time I_HCC = 2.5 μ A is 10 times smaller than the soft-start charging current I_SS = 25 μ A , the converter spends roughly 90% of the hiccup period completely OFF with zero switching. During the brief ~10% soft-start window, the 2 V cycle-by-cycle limit strictly caps the primary peak current. This keeps average power dissipation and thermal stress very low so the MOSFETs and transformer cannot overheat. If a permanent latch-off is required: If your system safety specs strictly forbid auto-retry, we can easily add a small external circuit that detects the fault and pulls the SS pin below 0.55 V . That will keep the outputs permanently disabled until VDD is power cycled. Regards, Govindhttps://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1697518/ucc5890qevm-125-doc-cert-ucc5881-emc-simulation-spice-modelFri, 13 Nov 2026 06:39:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d7488e5b-f36a-4c7e-b1da-e472a6bfcdf9hu xiankePart Number: UCC5890QEVM-125-DOC-CERT hello is there any update of this spice model ?UCC5890QEVM-125-DOC-CERThttps://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1693449/am6442-ondie-parasitics-of-am6442-for-power-aware-si-simulation/6538151Fri, 13 Nov 2026 02:22:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2c5b9d8a-35d5-452f-9d9e-9d143c6a1cc2Kallikuppa SreenivasaHello Amaud [quote userid="678438" url="~/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1693449/am6442-ondie-parasitics-of-am6442-for-power-aware-si-simulation/6537372"] Hello Sreenivasa, I’m following up regarding my query and the inputs from the Simulation Expert. Have you received any updates you could share with me? Thank you in advance for your help. Best regards, [/quote] The expert has submitted the reply. Please let me know if you have any additional queries. Regards, Sreenivasahttps://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1697477/pspice-for-ti-product-installationFri, 13 Nov 2026 01:17:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:b79b31a9-7935-4688-8868-7eff15674ea7wai hong cheePart Number: PSPICE-FOR-TI Hi, please help on my installation as i get the following pop up.PSPICE-FOR-TIhttps://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1693449/am6442-ondie-parasitics-of-am6442-for-power-aware-si-simulation/6538092Fri, 13 Nov 2026 00:19:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:b0d6d527-f4ad-4405-8613-b17db7d0b63aLogan HansenHi Arnaud, Here are the PDS capacitor and PDS resistor values for the AM64x, and how to adjust them for your simulation setup. We don't have a value for the short resistor to provide. Our AM64x simulations model the PDS capacitor and PDS resistor only. If you run into problems leaving out the short resistor in your tool, let us know and we can look at it with you. How the values are obtained: AM64x has 58 DDR buffers on VDDS_DDR supply rail: 22 Data buffers (11 for each byte lane) and 36 Command/Address. The on-die capacitance for the part of the interface you are simulating is defined by the formula: Cvddq_c = vddq_c*num_io/num_total_io , where: vddq_c = 6.985 nF (The total on-die decoupling capacitance on the DDR supply rail) num_total_io = All buffers on supply rail num_io = The number of buffers in the group you are simulating. Each buffer has its own share of the rail's decoupling capacitance. Each data byte lane has 11 (8 DQ, DM, DQS+, DQS-) and the Command/Address region has 36. The Command/Address count includes buffers that LPDDR4 doesn't use (like ACT_n, BG0/1, PAR) because their decoupling is still on the same rail. Data: If you are simulating B0 or B1, use num_io = 11, if you are simulating B0 and B1, use num_io = 22. Example: Simulating for B0 Cvddq_c = vddq_c*num_io/num_total_io = (6.985e-09 * 11)/58 = 1.32474e-9 PDS Capacitor = Cvddq_c = 1.3247 nF PDS Resistor = Rvddq_c = 25.00366 mΩ Command/Address If you are simulating Command/Address, use num_io = 36. Example: Simulating Command/Address Cvddq_c = vddq_c*num_io/num_total_io = (6.985e-09 * 36)/58 = 4.3355e-9 PDS Capacitor = Cvddq_c = 4.3355 nF PDS Resistor = Rvddq_c = 25.00366 mΩ Summary: Simulating num_io PDS capacitor PDS resistor Data, B0 or B1 11 1.3247 nF 25.00366 mΩ Data, B0 and B1 22 2.6495 nF 25.00366 mΩ Command/Address 36 4.3355 nF 25.00366 mΩ All 58 buffers 58 6.985 nF 25.00366 mΩ AM62x DDR Board Design and Layout Guidelines (Rev. C) on page 33 lists on-die values that can be used for AM62x and AM62L simulations. These values are shown in the table above and can also be used for AM64x, as it has the same DDR interface/signal set as AM62x. Let us know if you have any questions. Best Regards, Loganhttps://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1651682/pspice-for-ti-lm74910h-q1-pspice-simulation/6537480Thu, 12 Nov 2026 12:45:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:6f745134-f460-455f-bcaf-00b9dee536e6Shiven DhirHi Kazuki, Yes, I will share the model file with you. It will be LM74910Q1 and not LM74910HQ1. Only difference will be in sleep mode. I think customer is not using it so it should be fine. Regards, Shiven Dhirhttps://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1691980/pspice-for-ti-orcommn-12005-license-txt-not-created-after-reinstall---installer-url-pcb-cadence-com-returns-nxdomain/6537477Thu, 12 Nov 2026 12:38:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e308bc1c-eb36-4079-bf43-43105af4796dKarthik ArumughamStuck with the same issue.https://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1693449/am6442-ondie-parasitics-of-am6442-for-power-aware-si-simulation/6537372Thu, 12 Nov 2026 10:24:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c3e3a2e0-d8bc-49d0-80b9-7f4e8342df99ArnaudHello Sreenivasa, I’m following up regarding my query and the inputs from the Simulation Expert. Have you received any updates you could share with me? Thank you in advance for your help. Best regards, Arnaudhttps://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1696260/ucc28950-ucc28950-hiccup-mode/6537255Thu, 12 Nov 2026 08:13:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:22dffeb6-cb69-414c-8d27-6d251479b9f4furkan ülgerthank you for information. So If a short circuit happens in converter , primary current voltage will exceed 2V and IC will shut down then Will it try to operate again ? and Will it be stuck at this condition ? or during initial soft start cycle-bycycle protection detects the over current again after PWM pulses then IC will not to try to operate again . Which one does happen ?https://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1651682/pspice-for-ti-lm74910h-q1-pspice-simulation/6537073Thu, 12 Nov 2026 04:07:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:6fc8e4ed-91b1-46a9-9443-198070f53667Kazuki ItohHi Shiven, Do you have any update on this? Is the PSpice model release schedule on track? Best regards, Kazuki Itohhttps://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1696023/am263p4-am263px-i2c-communication-with-adxl382-fails/6536970Thu, 12 Nov 2026 01:54:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:05d24f12-e440-4b96-96d5-d909c1dd9e17Nilabh AnandHi Can you share the full syscfg file, what is the self address of I2c master, this is one option in syscfg.https://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1696023/am263p4-am263px-i2c-communication-with-adxl382-fails/6536519Wed, 11 Nov 2026 16:53:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ec60e9df-92f8-47c8-9f6e-094ec94cca6fFleenorHi Sreerag, Thanks for providing the details! The root cause is now narrowed to a specific register behavior: the I2C0 BB (Bus Busy) bit only clears on a STOP condition — or when the module is forced into reset — it does not self-clear just because SCL/SDA are idle-high. 1. Why BB stays 1 despite idle-high SCL/SDA Per the ICSTR field description: BB is set on a START condition or when the controller detects SCL low, and "BB is clear to 0 after reception of a 'stop' condition. BB is kept to '0' regardless of SCL state when the I2C is in reset [IRS_=0]." 1 Since your controller has never completed a transaction (no START was ever driven), there has been no STOP to clear BB. The bit got latched at some point — most likely by a transient SCL-low condition sampled during pad/clock bring-up — and with the current idle-high levels alone, nothing in the documented behavior will clear it. The only two documented ways to clear BB are (a) a STOP condition, which can't happen without a prior START, or (b) putting the module back into reset (IRS_=0). 2. Controller-side cause: this is a deadlock, not a bus fault The ICSTR Arbitration-Lost (AL) field states: "The Arbitration Lost flag bit is set to 1 when the device in the 'controller' mode... attempts to start a transfer while BB [bus busy] is 1." 2 This explains your scope result directly — the controller sees BB=1, refuses to drive a START/SCL at all, and the transfer aborts before any clock edge appears. This matches "probe status = -1" with zero SCL activity. Why BB never got cleared by your prior reset/reinit attempts is the open question. Two controller-side requirements are relevant: IRS_ (ICMDR bit 5, "I2C Reset Not") : setting this to 0 puts the I2C in reset and, per the TRM, resets "all status bits in ICSTR... to default values" 3 — this is the documented mechanism to force BB back to 0. ICPSC, ICCLKL, ICCLKH (prescaler and clock divider registers) must be written only while IRS_=0 — each register description states "must be initialized while the I2C is still in reset [IRS_=0]" 4 5 6 . 3. Steps to clear BB and get a START/SCL Read ICMDR directly and confirm the current IRS_ bit (bit 5) state. Force IRS_ = 0 (module reset). Immediately re-read ICSTR — BB should now read 0, per the documented reset behavior. While still in reset (IRS_=0), (re)write ICPSC, ICCLKL, ICCLKH for your target 100 kHz rate — do not skip this, since these are only valid to program in this state. With SCL/SDA confirmed idle-high (as you've already measured), set IRS_ = 1 to release reset. Immediately re-read ICSTR. If BB sets again the instant IRS_ releases, scope SCL precisely at that transition (not just steady-state idle) — this would point to the input qualifier (QUAL_SEL) sampling a glitch at release, rather than a true bus fault. Only after ICSTR reads BB=0 post-reset, re-run I2C_probe() and re-scope A13/B13 to confirm a START condition and clock pulses now appear. Follow up: Can you share the ICMDR register value (confirming the current IRS_ state) and whether BB clears after you force IRS_ = 0 directly via register write (rather than through the driver's close/open calls)? Resources: AM263Px TRM — I2C_ICSTR, BB field AM263Px TRM — I2C_ICSTR, AL field AM263Px TRM — I2C_ICMDR, IRS field AM263Px TRM — I2C_ICPSC AM263Px TRM — I2C_ICCLKL AM263Px TRM — I2C_ICCLKH Best Regards, Zackary Fleenorhttps://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1695256/interconnect-studio-cannot-open-it/6536503Wed, 11 Nov 2026 16:44:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:879469f2-6cfa-416a-989b-822b019fa788Nikki DengelHi Han, Did you try un-installing and re-installing the software? Unfortunately, TPLD2001-Q1 is only in InterConnect Studio 1.8.1. You can use version 1.6.0 to get started with the design in TPLD2001 (the design process is identical, and the difference is only when you order devices). What kind of computer and operating system are you using? I can try to investigate whether there are any known issues with a specific computer setup. For example, InterConnect Studio often doesn't work well with ARM-based processors such as Snapdragon. If you are not in a rush, we also have an online version of InterConnect Studio. However, the online version is down right now as we work to repair the server issue I mentioned previously. We hope to have it back online soon. Regards, Nikkihttps://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1693554/dp83td510e-podl-evm-designing-for-implementing-10base-t1l-technology-into-a-new-mpu/6536324Wed, 11 Nov 2026 14:06:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:8e11de2c-359b-4c5d-bc5b-db8d424f85faJohn KriskeyHello Vivann Thank you for the update - I believe we are going in a different direction using an ethernet switch instead of using a LAN based multiplexer All the besthttps://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1697034/dlp4710-dlp4710-blazed-grating-condition-not-satisfiedWed, 11 Nov 2026 13:16:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:3ff5d980-2f18-4394-8c04-229e51a5258fIKA OKTAVIA SURYANIPart Number: DLP4710 Hello, I am using a DLP4710 with 5.4µm pixel pitch, Illumination source is a 405nm laser (gaussian beam). I am trying to align the DMD to get a blazed grating condition. During the testing, all pixels in the 'on' state with no projection optics after the DMD. I scanned the illumination angle from 20-50 degree. However, I get four to two pronounced diffraction orders instead of one. I tried to reach the blazing condition to maximize the diffraction efficiency. Any suggestions related to this issue are appreciated.DLP4710https://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1696022/ucc28704---pspice-for-ti-error-orpsim-15116-unable-to-find-library-file-74ac11000-lib/6536270Wed, 11 Nov 2026 12:57:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:17dd885b-8aab-405a-a173-cb6343e621a2Govind RaiHi, your issue has resolved? regards, Govindhttps://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1696062/tps1200-q1-calc-webench-power-designer-fails-to-simulate-any-design/6536154Wed, 11 Nov 2026 10:13:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f1db04cb-a300-4e48-ab03-24f3f7b217f6Sateesh GoudappanavarHi Dan Winkelstein , Please be informed that the above reported issue is resolved. Please verify your design and simulations on WEBENCH Power Designer. Please feel free to reach out to us if you face any further issues. Thank you Best Regards, Sateesh A Ghttps://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1696763/tlv61046a-simulations-not-working/6536148Wed, 11 Nov 2026 10:11:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:a5f14443-6af1-4fd8-bd5e-c161c5415f9bSateesh GoudappanavarHi Frank Strazzabosco Please be informed that the above reported issue is resolved. Please verify your design and simulations on WEBENCH Power Designer. Please feel free to reach out to us if you face any further issues. Thank you Best Regards, Sateesh A Ghttps://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1695891/tps6104xcalc-webench-simulations-not-work-at-all/6536146Wed, 11 Nov 2026 10:10:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:1c08dcd7-f041-4000-b4b4-b0252f38522bSateesh GoudappanavarHi Frank Strazzabosco & Shipeng Cheng , Please be informed that the above reported issue is resolved. Please verify your design and simulations on WEBENCH Power Designer. Please feel free to reach out to us if you face any further issues. Thank you Best Regards, Sateesh A Ghttps://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1696113/lm3478-88-boost-calc-lm3478-simulated-current-exceeds-calculated-limit-during-load-transient/6536143Wed, 11 Nov 2026 10:08:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f554b0fc-1468-41e9-86cf-57033bf30460Hassan JamalHi Fachini, Thank you for sharing the additional waveforms. With RFA = 95.3 kΩ, the LM3478 nominal switching frequency should be approximately 200 kHz. The device includes short-circuit protection that reduces the switching frequency by a factor of five when the ISEN voltage exceeds the typical 343 mV threshold. However, this mechanism alone does not explain the approximately 10 kHz switching pattern observed in your simulation. Additionally, the current-limit threshold decreases with increasing duty cycle due to slope compensation. Therefore, the observed 7.73 A inductor-current peak is significantly higher than the calculated normal current limit. The waveforms show that DR remains high for an unusually long interval while the inductor current increases. I would recommend to verify this behavior on the test board because the simulation model might need some verification. https://www.ti.com/tool/LM3478EVAL Best regards, Hassan