Other Parts Discussed in Thread: CC2674R10, CC1354P10,
Tool/software:
Hi all,
I'm using TI Arm Clang Compiler v3.2.2.LTS, CCS v12.4, CC2674R10 (Cortex M33, Armv8-M)
building a project based on project_zero example
trying to use code originally written for armcl
this code uses _disable_interrupts() and _restore_interrupts() intrinsics to protect critical sections: uint32_t savevar;
savevar = _disable_interrupts(); // get current interrupt state and disable interrupts (TI ARM Compiler intrinsic)
// critical code...
_restore_interrupts(savevar); // restore interrupt state (TI ARM Compiler intrinsic)
tiarmclang does not support these intrinsics, but provides the ti_compatibility.h header file that should convert them to a tiarmclang compatible form:/******************************************************************************/
/* Disable interrupts */
/******************************************************************************/
static __inline__ uint32_t __attribute__((always_inline))
_disable_interrupts(void)
{
#if __ARM_ARCH_PROFILE == 'M' && __ARM_ARCH == 6
return _disable_IRQ();
#elif __ARM_ARCH_PROFILE == 'M' && __ARM_ARCH == 7
uint32_t res = 0;
__asm volatile ("MRS %0, FAULTMASK" : "=r" (res) : : );
__asm volatile ("CPSID F" : : : );
return res;
#elif __ARM_ARCH >= 7
uint32_t res = _get_CPSR();
__asm volatile ("CPSID IF" : : : );
return res;
#else
return 0
#endif
}
/******************************************************************************/
/* Restore interrupts */
/******************************************************************************/
static __inline__ void __attribute__((always_inline))
_restore_interrupts(uint32_t x)
{
#if __ARM_ARCH_PROFILE == 'M' && __ARM_ARCH == 6
__asm volatile ("MSR PRIMASK, %0" : : "r" (x) : );
#elif __ARM_ARCH_PROFILE == 'M' && __ARM_ARCH == 7
__asm volatile ("MSR FAULTMASK, %0" : : "r" (x) : );
#elif __ARM_ARCH >= 7
__asm volatile ("MSR CPSR_fc, %0" : : "r" (x) : );
#endif
}
The compiler takes the path "#elif __ARM_ARCH >= 7" and fails on _restore_interrupts() with "invalid operand for instruction":
C:\ti\ccs1240\ccs\tools\compiler\ti-cgt-armllvm_3.2.2.LTS\include\c\ti_compatibility.h:1529:21: error: invalid operand for instruction __asm volatile ("MSR CPSR_fc, %0" : : "r" (x) : ); ^ <inline asm>:1:5: note: instantiated into assembly here MSR CPSR_fc, r0 ^
The Armv8-M Architecture Reference Manual does not even mention a CPSR register, let alone CPSR_fc.
Is this code (and with it the whole header file) applicabe to Arm v8-M at all?
Is there already a fix available for this problem?
Or is there an alternative with the same functionality?
I found CPUcpsid() in driverlib's cpu.h: it also returns the original interrupt enable state, but there is no function to restore it to that state.
Regards,
Wolfgang