CC1352P: CC1352P Ripple on internal DCDC

Ömer Ekinci

Prodigy 35 points

Part Number: CC1352P

We have custom board with Power block based on LAUNCHXL-CC1352P and application based on simple peripheral,

Our problem is some of boards starts consumpting too much current with a ripple on DCDC output.

We tried use empty project to eliminate software cause and result is same. DCDC enabled by example default.

Chip revision: CC1352P1F3 Rev:E

SDK: 4.40

Ripple on DCDC Output (1-2 different boards, 3 Peaks zoomed in)

Current Consumption(Avarage rises from ~30 uA's to 2-3 mA's), Periodic consumption due problem ~2.5mS Ipeak 19mA

What can be cause some of boards starts to do this behavior after a while?

Thank You!

over 2 years ago

0 Vegard H over 2 years ago

TI__Expert 4560 points

Hi Omer
Can you share the layout of the board around the DCDC components? Improper ground return paths can lead to not ideal behavior, so it is good to verify that the layout is good first. before I do more debugging.
Vegard

0 Ömer Ekinci over 2 years ago in reply to Vegard H

Prodigy 35 points

Hi Vegard, i'm glad for your response,

Here:

0 fredrikgk over 2 years ago in reply to Ömer Ekinci

Expert 2140 points

That does not look too good!

Take a look at www.ti.com/lit/pdf/swra640 .

+1 Vegard H over 2 years ago in reply to Ömer Ekinci

TI__Expert 4560 points

It seems like the ground connection between the DCDC cap and the chip is not ideal. The DCDC components should be as close as possible to the chip for ideal performance. You can read more in section 4.7 of the Hardware Configuration and PCB Design Considerations app note:
https://www.ti.com/lit/an/swra640e/swra640e.pdf

Why have you added the 47 uF capacitor?

Vegard

0 Ömer Ekinci over 2 years ago in reply to Vegard H

Prodigy 35 points

You're right, we missed it. Our DCDC componenets far from DCDC pin.

1. In our project we use ble at 20dB with long periods, and avarage consumption is ~30uA with 100mA peaks. But our battery caracteristic permits 10mA continious and 50mA peaks. Because of that we added an optional 47uF to VDDR for just in case scenerio. Should we remove it?

2. If we use Global LDO Mode how much nominal and peak current we must supply to VDDR pin. And how much efficiency loss we should expect?

Thank you for your answers!

+1 Vegard H over 2 years ago in reply to Ömer Ekinci

TI__Expert 4560 points

I don't think the 47 uF capacitor should be a problem here.

The efficiency of the GLDO should be around 93.3% at higher currents, but will drop down in lower currents. You don't need to supply the VDDR pin with any current since the internal GLDO will take care of it, except if you want to use external regulator mode.

0 fredrikgk over 2 years ago in reply to Vegard H

Expert 2140 points

The GLDO efficiency is dependent on the input voltage. If VDDS is 3.3 V, the efficiency will never be higher than 50%. 93% efficiency is theoretical maximum for VDDS = 1.8V. If that is the supply voltage it makes more sense to run in External Regulator mode.

0 Vegard H over 2 years ago in reply to fredrikgk

TI__Expert 4560 points

Thanks Fredrik, didn't have all the correct info there.

Vegard

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CC1352P: CC1352P Ripple on internal DCDC