customer found a phenomenon. the Slow clock will stop on some chip when the Frequency accuracy exceed 150ppm because of the C load is not match. when the capacitor matched, the phenomenon is gone.
The crystal spec is compliant with our Datasheet's requirement on the Cload and ESR.
as the claim, for the BLE stack, 500ppm is acceptable.
so customer would like to understand the reason behind, SW configuration? or the HW.