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CC2642R: 32k768 crystal stop oscillate when the frequency accuracy exceed 150ppm.

Part Number: CC2642R


customer found a phenomenon. the Slow clock will stop on some chip when the Frequency accuracy exceed 150ppm because of the C load is not match. when the capacitor matched, the phenomenon is gone. 

The crystal spec is compliant with our Datasheet's requirement on the Cload and ESR. 

as the claim, for the BLE stack, 500ppm is acceptable. 

so customer would like to understand the reason behind, SW configuration? or the HW. 

BR. Albin

  • Hi Albin,

    It could be a crystal start up problem due to load capacitor mismatch. Are they measuring the clock on a DIO?

    How much do they change the load capacitor to start up the clock again?

    It is correct that the limit is 500ppm. Can they check to see if it works by switching to RCOSC_LF?


  • Hi Farrukh

    thanks for reply.

    they found the issue (3% failure rate) after SMT. the board keep reset unexpected. after read the flag and found it is Clock loss.

    Yes, they measure the DIO and ask the crystal vendor to tune the C load. it is sure the test/tune method is okay. 

    Sure, RCOSC_LF is working good. 

    C1/C2=10pF, Clock stop on some of the board. 150ppm

    C1/C2=18pF. 15 ppm. working good. 

    as you mentioned, "crystal start up problem due to load capacitor mismatch". Could elaborate more about the reason?  


  • Hi Albin,

    With C1,C2 = 18pF, the CL becomes 9pF, which is what the datasheet states should be, correct?


  • Hi Farrukh, 

    Yes, dual 18pF is right design. and startup have no problem. 

    they question is if mismatch, e.g. 150ppm with dual 10pF, why osc circuit has startup issue? 

    BR. Albin