CC2640R2F: CC2640R2F I2S Samplestamp Generator function

Hi Alex,

I have done something similar before with this exact audio codec but a different SimpleLink device (I used CC2652R). I could not find back my code (it was 3 years ago) but I hope it will be of interest for you anyway.

Solution summary

• The frequency correction is made on the Rx side - no modification on the Tx side
• The frequency of the audio clock is given by the average clock frequencies across the time.
  

In our case, only two frequencies will be used, the “initial frequency” and the closest higher or lower frequency reachable.

• Based on the number of samples consumed between the receptions of two audio frames from the radio, the frequency of the audio clock is adapted i.e. time spent inputting one or the other frequency to the codec.
• The number of samples consumed is read using the sample stamp generator of the I2S module. For the moment the read is triggered in the radio Rx callback.

Solution implementation

First of all, the TLV320AIC3254 should configured as the I2S master (the CC2640R2F being I2S "slave"). This means the CC2640R2F has to input an high frequency MCLK clock to the TLV320AIC3254. I recommend to produce this clock using a timer of the CC2640R2F.
Note 1: The SimpleLink Audio Plugin showcases this for CC26x2. I would recommend taking a look at it. See https://dev.ti.com/tirex/explore/node?node=A__AFfZCYCdhZoqa2UTNzEQxg__com.ti.SIMPLELINK_AUDIO_PLUGIN__RW99gST__LATEST
Note 2: The board with the TLV320AIC3254 (CC3200AUDBOOST I believe) requires an hardware modification (remove a capa and add a jumper wire) to enable this. See https://dev.ti.com/tirex/content/simplelink_audio_plugin_3_30_00_06/docs/Quick_Start_Guide.html#hardware-setup under "(Optional) I2S Slave Mode"

Second, configure the PLL of the TLV320AIC3254 in order to require the lowest clock frequency possible from the CC26x2/CC13x2 device. That way, the step between two frequencies is as little as possible.
In my example, the clock inputted to the TLV320AIC3254 is 250 kHz. The closest higher reachable frequency is 252.6 kHz. The closest lower reachable frequency is 247.4 kHz.
Note 3: At this stage, your system should have the same performances like before (i.e. the clock drift issue should still be there but the audio quality should be identical).

Third, implement the logic for frames counting.

• at the reception of each new audio frame from the radio, we determine (using the sample stamps generator) the number of audio samples consumed
• the number of audio samples consumed is compared to the number of audio samples received
• if more audio samples are received than consumed, then we increase the MCLK frequency. On the contrary, if less audio samples are received than consumed, then we decrease the MCLK frequency.
• To decrease/increase MCLK frequency we modify the values of numberOfCyclesModified and directionOfModification

Fourth, implement a way to slightly modify the MCLK frequency. The MCLK frequency can be modified by increasing/decreasing the prescaler value of the timer. The frequency average is done over 10,000 frames of samples (i.e. 60,000 samples, or 1.36 seconds at 44.1 kHz). The MCLK frequency can be changed at the beginning of every frames. In practice, we change the MCLK frequency 2 times maximum per 10,000 frames. We use a counter counting from 10.000 down to 0 – the counter is set back to 10.000 when reaching 0. During the 10,000-numberOfCyclesModified periods MCLK frequency is 250kHz. During the numberOfCyclesModified remaining periods, the MCLK frequency is 252.6 kHz or 247.4 kHz – based on the value of directionOfModification.

I hope this will help,

Best regards,