Tool/software:
Hello,
We have developed one application in which CC2642 act as pass through. It connects mobile application over Bluetooth Low Energy and parses the command and sent it to Main MCU via SPI lines.
Clock Freq - 3 MHz
Setting - POL0 PHA1
Clock Polarity - low
Clock Phase - rising edge
The CC2642 act as SPI Slave device and Main MCU is SPI Master. CS is configured as Software driven where CC2642 waits for Master Ready(HW Pin Interrupt) before calling SPI Transfer(). Because this device runs on Battery, to save power we have two handshaking signal for SPI, One is SRDY - Slave Ready and another is MRDY - Master Ready. Anyone can initiate the request to other by asserting respective line first and then waits for other to assert other pair of it to Logic Level low. This assertion is detected by PIN HW Interrupt where we starts time and call SPI Transfer will appropriate data. One the MRDY gets de-asserted, CC2642 understands that there might be data available as a response or a new request. This is understood by upper layer as it is following the protocol.
Recently we fixed a race condition in timeout timer (protocol timer for message exchange timeout) and MRDY assertion both happening simultaneously. ( I had earlier thread on community for the same). We had put the execution of MRDY de-assertion interrupt handler into Critical Section as this piece of code stopping Timer.
Recently we had observed that when we get a request from Main MCU, there is a bit flip in RX Buffer which makes the CRC error and packets getting dropped by CC2642 MCU. When we put MRDY interrupt code kept in Critical Section (Uses ICALL Api's), the frequency of occurrence is much greater.
We verified using Saleae Logic Pro 16 that the voltage levels and clock signals are proper. Please suggest do we need to have it seen on Oscilloscope?
Please help me guide on all possible scenarios where there can be a data corruption in SPI RX Buffer.
Thanks and Regards,
Chinmay Lotake