Part Number: CC2745P10-Q1
Other Parts Discussed in Thread: SYSCONFIG
Tool/software:
Hello TI Team,
I'm working with the CC2745P10-Q1 and trying to output the Low-Frequency RC Oscillator clock signal to DIO27 using the program code from the application note.
However, when I set the clockSrc, i won't work.
uint8_t clockSrc = 0xE; // No Signal
uint8_t clockSrc = 0xF; // No Signal
uint8_t clockSrc = 0x0; // Signal
uint8_t clockSrc = 0x1; // Signal
uint8_t clockSrc = 0x2; // Signal
What do I need to change in the code or configuration to activate the LF RC oscillator so that it can be routed to DTB0 (DIO27)?
Thank you very much for your support!
Best regards,
Lars Kuhn
Program Code:
/* INCLUDES
*/
#include <ti/drivers/GPIO.h>
#include DeviceFamily_constructPath(inc/hw_types.h)
#include DeviceFamily_constructPath(inc/hw_memmap.h)
#include DeviceFamily_constructPath(inc/hw_ckmd.h)
#include DeviceFamily_constructPath(inc/hw_ioc.h)
#include DeviceFamily_constructPath(inc/hw_pmctl.h)
// ...
int main()
{
// ...
/** Add the following after Board_init();
* Be sure IOID used below is not used by any entries in PIN or
* GPIO tables from the board files.
* The clock source can be switched with constant clockSrc.
*/
uint8_t clockSrc = 0xE; // for LF crystal clock
// drive output low first
GPIO_setConfig(27, GPIO_CFG_OUTPUT | GPIO_CFG_OUT_LOW);
// Configure the IOC.IOC19.PORTCFG MMR to select DTB
HWREG(IOC_BASE + IOC_O_IOC27) &= ~IOC_IOC19_PORTCFG_M;
HWREG(IOC_BASE + IOC_O_IOC27) |= IOC_IOC19_PORTCFG_DTB;
// Make sure the DTB mux selects in IOC (and if required in
// source clock IP) are reset that zero is driven on DTB0.
// ULLSEL mux select (select CKMD)
HWREG(IOC_BASE + IOC_O_DTBCFG) &= ~IOC_DTBCFG_ULLSEL_M;
HWREG(IOC_BASE + IOC_O_DTBCFG) |= 0x1 << IOC_DTBCFG_ULLSEL_S; // 0x1 to route CKMD to DTB0
// Enable IOC.DTBOE.EN0
HWREG(IOC_BASE + IOC_O_DTBOE) &= ~IOC_DTBOE_EN0_M;
HWREG(IOC_BASE + IOC_O_DTBOE) |= IOC_DTBOE_EN0_EN;
// select which clock (CKMD) to output on DTB0 (DTB[0])
HWREG(CKMD_BASE + CKMD_O_DTBCTL) &= ~CKMD_DTBCTL_CLKSEL_M;
HWREG(CKMD_BASE + CKMD_O_DTBCTL) |= (clockSrc) << CKMD_DTBCTL_CLKSEL_S;
// enable DTB output
HWREG(CKMD_BASE + CKMD_O_DTBCTL) &= ~CKMD_DTBCTL_EN_M;
HWREG(CKMD_BASE + CKMD_O_DTBCTL) |= CKMD_DTBCTL_EN;
// ...
}
