CC256XMS432BTBLESW: Reducing memory

Dhanya Unnikrishnan

Part Number: CC256XMS432BTBLESW
Other Parts Discussed in Thread: CC2564C

We build the "SPPLEDemo", but the binary size comes to 255KB (MSP432 is 256 KB). We need to add some more functionalities to the application but since the image is this big, it is not possible.

The option to configure (add or remove BT components) should be available in FBL build script "fbl_gen.pl" as per TI documents.

Also please let us know if we are doing anything wrong during build as the size seems too big.

But this file is missing in my installation directory. Could you please provide this script "fbl_gen.pl" as we need to reduce the memory size.

Library Used : Bluetopia_Full.lib

ROM Used : 0x0003fee4 (bytes)

RAM Used : 0x0000792c (bytes)

over 6 years ago

0 Emrys Maier over 6 years ago

TI__Guru* 96591 points

Hi Dhanya,
I'm not sure why this post keeps getting pushed to my forum -- I deal only with standard logic device (AND gates and similar analog functions)

I will contact the management of the group that owns the correct forum to see if I can get you some help.

0 dale over 6 years ago in reply to Emrys Maier

TI__Expert 6335 points

What tool are you using to compile the code? Are you optimizing the code in any way?

0 Dhanya Unnikrishnan over 6 years ago in reply to dale

Prodigy 80 points

Hi, We are using CCS. We just built the SPPLE demo provided from TI directly without changing any options; just to see how much the binary size comes to.

It came around 255 KB for Dual mode stack on CC2564C and

~200 KB when we use dual mode stack for 2564B

Please suggest on how to reduce the memory size.

0 dale over 6 years ago in reply to Dhanya Unnikrishnan

TI__Expert 6335 points

You can either set the build configuration for SPPLEDemo to Release, which has optimizations (right click on project->build configurations->set active->release)

Or you can use IAR as your compilation tool, IAR's compiler should reduce memory.

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CC256XMS432BTBLESW: Reducing memory