Hi,
My customer is implementing A2DP with below HW+SW.
HW: DK-TM4C129X + CC2564MODA
SW: www.ti.com/.../CC256XM4BTBLESW
Customer changed the A2DP demo so that single SSI (SPI master mode) is used to send the data.
(LRCLK is generated from BCLK by on board circuit)
Customer found SSI suddenly stops sending data and debugging it now.
It seems CPU stops writing new data to SSI TX FIFO and it results in SSI stop.
(Please see “Data write” sheet in attached excel sheet)
Customer also checked the period of audio data decoding and found the decoding period shows strange behavior.
(Please see “Decoding” sheet in attached excel sheet)
Time used for decoding varies (from short time to longer time).
It seems SSI stops when the decoding time gets longer than certain threshold.
Why decoding period varies?
What is potential root cause of the issue?
A2DP_190930.xlsx
Thanks and regards,
Koichiro Tashiro