CC2540 power-on default state of PIO pins

Hi,

After reset all the IOs are configured as inputs. Measuring HIGH on IOs suggests that some other

code configuring these IOs to act as output HIGH, In BLE stuck you can look for default board

configuration.

@Eng351, @Igor Sherer,

Thanks for your replies. I am checking the board default configuration and trying a few things.

@Fredrik K:

Why would you hit the verify button so soon? I am still checking and I will verify an answer when I get this problem solved. Thank you!

Kapil,

I verified the answer because what Eng351 wrote about the default GPIO configuration is correct. This information can also be found in the CC253x/4x Users Guide.

It is great that you will verify answers once you have confirmed they are working. Unfortunately not everybody does this, so threads tend to stay un-verified even though the original question(s) are answered.

/Fredrik

To elaborate Eng351's answer:

The default state of GPIOs when the chip is in reset (as it is during power up) is as inputs with pull-ups. There is no way to change this. As soon as the chip is fully powered up you can configure the pins to whatever you want.

/Fredrik

Thanks everyone for helping out so quickly!

Fredrick, appreciate your additional information. So the earliest that I can set the pins LOW is in "hal_board_cfg.h" in HAL_BOARD_INIT(). Despite this I do see a momentary HIGH on the pins when the board is switched ON. Just have to live with it.

I'll leave Eng351's answer as the verified answer where he first mentioned the default state to be INPUT with pull-ups.

PS: I have relays connected to these 4 pins. The side-effect of this momemtary HIGH is that the relays switch ON for a little bit on Power Up. Is there any way to prevent this? Anything I could do in hardware?

Thanks again, Kapil

Hi Kapil,

There could be a couple of hardware options, the background for these suggestions is the knowledge that the internal pull up resistor on the pad is 23k.

1) You could place an external resistor to ground that is much smaller than 23k, you would want to make sure the resistor was small enough that the resistive divided voltage appearing at the pin input is not around mid rail and causing excessive shoot through current to the input buffer of the chip.  The downside to this solution is that when you are outputting a high on the pin then there will be a lot of wasted current through the external resistor.

2) You could place external NMOS FETs which would have their gate control connect to another GPIO and the drain connected to the GPIO connected to the relay.  During power up you are assured that the FET gate control will be high thus causing the GPIO lines in question to be pulled down.  Once in a powered up state you would want to make sure the FET gate control was set to low.  For this solution you will have to ensure the external FET threshold voltage and rdson are appropriate, though I would think you'd have a lot of options.

I know both of these are a little painful but maybe one will work for you.

Regards,

BK

Hi Kapil, I assume you have a transistor between the I/O and the relay. You can add a voltage divider between the I/O and transistor base / gate to load down the pull up resistor and also ensure your transistor only switches when the I/O is high. If you are using an NPN and VCC = 3V, i would use say a 5K6 and 2K2:

GPIO ------[5K6]-------Base 

                                |

                               2K2

                                |

                              Gnd

Thank you  BugKing, Eng351!