LAUNCHXL-CC26X2R1: i2secho example has white noise at 8K sample rate

Trevor Hsu

Part Number: LAUNCHXL-CC26X2R1
Other Parts Discussed in Thread: CC3200AUDBOOST

Hi ,

We run the i2secho example in the latest SDK and it works properly. But when we change the sample rate to 8000, it will produce noise.

Thanks.

Trevor

over 6 years ago

0 Clément over 6 years ago

TI__Guru** 101460 points

Hi Trevor,

This noise could be produced by the “data processing” function added in the infinite loop of the echoThread. Can you verify if by commenting this portion of code you solve your problem?

Regards,

0 Trevor Hsu over 6 years ago in reply to Clément

Genius 4595 points

Hi Clément,

I have commented out this portion of code, it still has the noise at 8000 sample rate.

Thanks.

Trevor

0 Clément over 6 years ago in reply to Trevor Hsu

TI__Guru** 101460 points

Hi,

Just to be sure: are you experiencing "noise" or is it basically the lower audio-quality due to a lower sampling rate?

This could also be due to the Codec settings: are you using the i2secho example “as it” (just changing sampling frequency) or have you modified something else? (I2S slave, codec parameters…)

Regards,

0 Trevor Hsu over 6 years ago in reply to Clément

Genius 4595 points

Hi Clément,

I see if setting a lower sampling rate will affect the audio-quality. But regarding this kind of noise, it always occurs even if I unplug the Line-in cable. I think the root cause is related to I2S driver or Codec setting.

I didn't make any modification for i2secho.c, I just commented out the “data processing” function.

Thanks.

Trevor

0 Clément over 6 years ago in reply to Trevor Hsu

TI__Guru** 101460 points

Hi,

I don’t think that the driver could become noisy for a specific sampling rate. However, you can verify with a logic analyzer if the WS and SCK signals have the expected frequencies (you can also verify if you are getting the expected frame format).

I do think that the codec settings are not so good. You can try to modify these settings to get a better sound quality. Can you try for me the following settings? (you just need to paste this code in the switch of the function AudioCodec_config() in AudioCodec.c)

case 8000:  // Fs = 8kHz,  BCLK = input to PLL, BCLK = 256kHz
                AudioCodec_pageSelect(TI3254_PAGE_0);

                AudioCodec_regWrite(TI3254_CLK_MUX_REG, 0x13);       // PLL Clock is CODEC_CLKIN
                AudioCodec_regWrite(TI3254_CLK_PLL_P_R_REG, 0x80 | 0x10 | 0x02);    // PLL is powered up, P=1, R=2
                AudioCodec_regWrite(TI3254_CLK_PLL_J_REG, 0x008);     // J=8
                AudioCodec_regWrite(TI3254_CLK_PLL_D_MSB_REG, 0x00); // D = 0000
                AudioCodec_regWrite(TI3254_CLK_PLL_D_LSB_REG, 0x00); // D = 0000

                AudioCodec_regWrite(TI3254_CLK_NDAC_REG, 0x80 | 0x01);      // NDAC divider powered up, NDAC = 1
                AudioCodec_regWrite(TI3254_CLK_MDAC_REG, 0x80 | 0x04);      // MDAC divider powered up, MDAC = 4
                AudioCodec_regWrite(TI3254_DAC_OSR_MSB_REG, 0x00);   // DOSR = 0x0080 = 128
                AudioCodec_regWrite(TI3254_DAC_OSR_LSB_REG, 0x80);   // DOSR = 0x0080 = 128

                AudioCodec_regWrite(TI3254_CLK_NADC_REG, 0x80 | 0x01);      // NADC divider powered up, NADC = 1
                AudioCodec_regWrite(TI3254_CLK_MADC_REG, 0x80 | 0x04);      // MADC divider powered up, MADC = 4
                AudioCodec_regWrite(TI3254_ADC_OSR_REG, 0x80);       // AOSR = 128 ((Use with PRB_R1 to PRB_R6, ADC Filter Type A)
                break;

Best regards,

0 Trevor Hsu over 6 years ago in reply to Clément

Genius 4595 points

Hi Clément,

Regarding your codec setting, it seems to solve the noise problem. I will do more experimental testing.

About I2S driver & codec's setting, can it support the 4000 sampling rate???

Thanks.

Trevor

0 Clément over 6 years ago in reply to Trevor Hsu

TI__Guru** 101460 points

Hi Trevor,

Nothing will prevent the driver and the driver to work at 4 kHz.

On the driver’s side you basically need to set i2sParams.samplingFrequency to 4000.

On the codec’s side, it will probably require to tune the settings. For a first try, you can keep the same settings as the 8 KHz settings (the one I gave in my previous message). Then you can try the following settings:

case 4000:  // Fs = 4kHz,  BCLK = input to PLL, BCLK = 128kHz
                AudioCodec_pageSelect(TI3254_PAGE_0);

                AudioCodec_regWrite(TI3254_CLK_MUX_REG, 0x13);       // PLL Clock is CODEC_CLKIN
                AudioCodec_regWrite(TI3254_CLK_PLL_P_R_REG, 0x80 | 0x10 | 0x04);    // PLL is powered up, P=1, R=4
                AudioCodec_regWrite(TI3254_CLK_PLL_J_REG, 0x008);     // J=8
                AudioCodec_regWrite(TI3254_CLK_PLL_D_MSB_REG, 0x00); // D = 0000
                AudioCodec_regWrite(TI3254_CLK_PLL_D_LSB_REG, 0x00); // D = 0000

                AudioCodec_regWrite(TI3254_CLK_NDAC_REG, 0x80 | 0x01);      // NDAC divider powered up, NDAC = 1
                AudioCodec_regWrite(TI3254_CLK_MDAC_REG, 0x80 | 0x08);      // MDAC divider powered up, MDAC = 8
                AudioCodec_regWrite(TI3254_DAC_OSR_MSB_REG, 0x00);   // DOSR = 0x0080 = 128
                AudioCodec_regWrite(TI3254_DAC_OSR_LSB_REG, 0x80);   // DOSR = 0x0080 = 128

                AudioCodec_regWrite(TI3254_CLK_NADC_REG, 0x80 | 0x01);      // NADC divider powered up, NADC = 1
                AudioCodec_regWrite(TI3254_CLK_MADC_REG, 0x80 | 0x08);      // MADC divider powered up, MADC = 8
                AudioCodec_regWrite(TI3254_ADC_OSR_REG, 0x80);       // AOSR = 128 ((Use with PRB_R1 to PRB_R6, ADC Filter Type A)
                break;

I hope this will help.

Best regards,

0 Trevor Hsu over 6 years ago in reply to Clément

Genius 4595 points

Hi Clément,

Thanks for your help, I tried the 8K & 4K codec setting, it will produce the noise at 4KHz.

Trevor

0 Clément over 6 years ago in reply to Trevor Hsu

TI__Guru** 101460 points

Hi Trevor,

Actually we are reaching the limits of the Codec here. In fact, the lower the input clock frequency is (i.e. BCLK) the lower the quality is.

My best advice here is to increase the frequency of BCLK (keeping the same frequency for WCLK to keep the 4 kHz sampling rate). To do so, the best solution is to add “after padding”. I added 48 bits of after-padding (to have BCLK around 512 kHz). Here is my code:

This code to modify the settings of the I2S driver

    I2S_Params i2sParams;
    I2S_Params_init(&i2sParams);
    i2sParams.samplingFrequency =  SAMPLE_RATE; /* 4000 Hz*/
    i2sParams.afterWordPadding  =  48;
    i2sParams.fixedBufferLength =  BUFSIZE;
    i2sParams.writeCallback     =  writeCallbackFxn ;
    i2sParams.readCallback      =  readCallbackFxn ;
    i2sParams.errorCallback     =  errCallbackFxn;
    i2sHandle = I2S_open(Board_I2S0, &i2sParams);

This code to modify the settings of the Codec

        case 4000:  // Fs = 4kHz,  BCLK = input to PLL, BCLK = 512kHz (48 bits of after-padding must be added)
                        AudioCodec_pageSelect(TI3254_PAGE_0);

                        AudioCodec_regWrite(TI3254_CLK_MUX_REG, 0x13);       // PLL Clock is CODEC_CLKIN
                        AudioCodec_regWrite(TI3254_CLK_PLL_P_R_REG, 0x80 | 0x10 | 0x04);    // PLL is powered up, P=1, R=4
                        AudioCodec_regWrite(TI3254_CLK_PLL_J_REG, 0x036);     // J=54
                        AudioCodec_regWrite(TI3254_CLK_PLL_D_MSB_REG, 0x00); // D = 0000
                        AudioCodec_regWrite(TI3254_CLK_PLL_D_LSB_REG, 0x00); // D = 0000

                        AudioCodec_regWrite(TI3254_CLK_NDAC_REG, 0x80 | 0x12);      // NDAC divider powered up, NDAC = 18
                        AudioCodec_regWrite(TI3254_CLK_MDAC_REG, 0x80 | 0x0C);      // MDAC divider powered up, MDAC = 12
                        AudioCodec_regWrite(TI3254_DAC_OSR_MSB_REG, 0x00);   // DOSR = 0x0080 = 128
                        AudioCodec_regWrite(TI3254_DAC_OSR_LSB_REG, 0x80);   // DOSR = 0x0080 = 128

                        AudioCodec_regWrite(TI3254_CLK_NADC_REG, 0x80 | 0x12);      // NADC divider powered up, NADC = 18
                        AudioCodec_regWrite(TI3254_CLK_MADC_REG, 0x80 | 0x0C);      // MADC divider powered up, MADC = 12
                        AudioCodec_regWrite(TI3254_ADC_OSR_REG, 0x80);       // AOSR = 128 ((Use with PRB_R1 to PRB_R6, ADC Filter Type A)
                        break;

Note: these settings cannot be used on CC32XX (this after padding is not allowed)

Best regards,

0 Trevor Hsu over 6 years ago in reply to Clément

Genius 4595 points

Hi Clément,

Sorry,what is the lower the input clock frequency of the codec? could you help to replay it again.

Regarding your latest setting, the noise still exists(but it get smaller).

Our custom board, the input clock can be changed to MCLK, if we use MCLK as the input clock, could we solve the noise problem at 4KHz?

Thanks.

Trevor

0 Clément over 6 years ago in reply to Trevor Hsu

TI__Guru** 101460 points

Hi,

If you can change the input clock to MCLK (this is not possible, or at least not so easy on the CC3200AUDBOOST - on CC3200AUDBOOST MCLK and BCLK are shorted), you can definitely improve your sound quality. The codec is already set in order to have MCLK as an input. If not the following line sets the codec for I2S mode, MCLK as input clock, 16-bit samples, WCLK and BCLK are inputs of the Codec:

AudioCodec_regWrite(TI3254_AUDIO_IF_1_REG, 0x00);

Now, you have to activate MCLK on the driver's side: to do so you have to chose a pin for MCLK (CC26X2R1_LAUNCHXL_I2S_MCLK must be set to a valid pin). Then you can chose the MCLK frequency using i2sParams.MCLKDivider (MCLK's frequency is 48MHz/MCLKDivider).

If you are interested, I have calculated the following parameters for your codec (assuming MCLK=1MHz):

        case 4000:  // Fs = 4kHz,  MCLK = input to PLL, MCLK = 1MHz (MCLKDivider = 48)
                        AudioCodec_pageSelect(TI3254_PAGE_0);

                        AudioCodec_regWrite(TI3254_CLK_MUX_REG, 0x13);       // PLL Clock is CODEC_CLKIN
                        AudioCodec_regWrite(TI3254_CLK_PLL_P_R_REG, 0x80 | 0x10 | 0x04);    // PLL is powered up, P=1, R=4
                        AudioCodec_regWrite(TI3254_CLK_PLL_J_REG, 0x020);     // J=32
                        AudioCodec_regWrite(TI3254_CLK_PLL_D_MSB_REG, 0x00); // D = 0000
                        AudioCodec_regWrite(TI3254_CLK_PLL_D_LSB_REG, 0x00); // D = 0000

                        AudioCodec_regWrite(TI3254_CLK_NDAC_REG, 0x80 | 0x19);      // NDAC divider powered up, NDAC = 25
                        AudioCodec_regWrite(TI3254_CLK_MDAC_REG, 0x80 | 0x0A);      // MDAC divider powered up, MDAC = 10
                        AudioCodec_regWrite(TI3254_DAC_OSR_MSB_REG, 0x00);   // DOSR = 0x0080 = 128
                        AudioCodec_regWrite(TI3254_DAC_OSR_LSB_REG, 0x80);   // DOSR = 0x0080 = 128

                        AudioCodec_regWrite(TI3254_CLK_NADC_REG, 0x80 | 0x19);      // NADC divider powered up, NADC = 25
                        AudioCodec_regWrite(TI3254_CLK_MADC_REG, 0x80 | 0x0A);      // MADC divider powered up, MADC = 10
                        AudioCodec_regWrite(TI3254_ADC_OSR_REG, 0x80);       // AOSR = 128 ((Use with PRB_R1 to PRB_R6, ADC Filter Type A)
                        break;

I hope this will help,

Best regards,

0 Trevor Hsu over 6 years ago in reply to Clément

Genius 4595 points

HI Clément,

I did some re-work on CC3200AUDBOOST, we have changed input clock to MCLK.

Update the test result:

If I using the following setting, it has the smaller noise(but the quality is good), the result is the same with "48 bits of after-padding"

        case 4000:  // Fs = 4kHz,  MCLK = input to PLL, MCLK = 1MHz (MCLKDivider = 48)
                 AudioCodec_pageSelect(TI3254_PAGE_0);

                 AudioCodec_regWrite(TI3254_CLK_MUX_REG, 0x13);       // PLL Clock is CODEC_CLKIN
                 AudioCodec_regWrite(TI3254_CLK_PLL_P_R_REG, 0x80 | 0x10 | 0x04);    // PLL is powered up, P=1, R=4
                 AudioCodec_regWrite(TI3254_CLK_PLL_J_REG, 0x020);     // J=32
                 AudioCodec_regWrite(TI3254_CLK_PLL_D_MSB_REG, 0x00); // D = 0000
                 AudioCodec_regWrite(TI3254_CLK_PLL_D_LSB_REG, 0x00); // D = 0000

                 AudioCodec_regWrite(TI3254_CLK_NDAC_REG, 0x80 | 0x19);      // NDAC divider powered up, NDAC = 25
                 AudioCodec_regWrite(TI3254_CLK_MDAC_REG, 0x80 | 0x0A);      // MDAC divider powered up, MDAC = 10
                 AudioCodec_regWrite(TI3254_DAC_OSR_MSB_REG, 0x00);   // DOSR = 0x0080 = 128
                 AudioCodec_regWrite(TI3254_DAC_OSR_LSB_REG, 0x80);   // DOSR = 0x0080 = 128

                 AudioCodec_regWrite(TI3254_CLK_NADC_REG, 0x80 | 0x19);      // NADC divider powered up, NADC = 25
                 AudioCodec_regWrite(TI3254_CLK_MADC_REG, 0x80 | 0x0A);      // MADC divider powered up, MADC = 10
                 AudioCodec_regWrite(TI3254_ADC_OSR_REG, 0x80);       // AOSR = 128 ((Use with PRB_R1 to PRB_R6, ADC Filter Type A)
                 break;

I also tried the previous setting, without noise, but the quality is very bad.

case 4000:  // Fs = 4kHz,  BCLK = input to PLL, BCLK = 128kHz
                AudioCodec_pageSelect(TI3254_PAGE_0);

                AudioCodec_regWrite(TI3254_CLK_MUX_REG, 0x13);       // PLL Clock is CODEC_CLKIN
                AudioCodec_regWrite(TI3254_CLK_PLL_P_R_REG, 0x80 | 0x10 | 0x04);    // PLL is powered up, P=1, R=4
                AudioCodec_regWrite(TI3254_CLK_PLL_J_REG, 0x008);     // J=8
                AudioCodec_regWrite(TI3254_CLK_PLL_D_MSB_REG, 0x00); // D = 0000
                AudioCodec_regWrite(TI3254_CLK_PLL_D_LSB_REG, 0x00); // D = 0000

                AudioCodec_regWrite(TI3254_CLK_NDAC_REG, 0x80 | 0x01);      // NDAC divider powered up, NDAC = 1
                AudioCodec_regWrite(TI3254_CLK_MDAC_REG, 0x80 | 0x08);      // MDAC divider powered up, MDAC = 8
                AudioCodec_regWrite(TI3254_DAC_OSR_MSB_REG, 0x00);   // DOSR = 0x0080 = 128
                AudioCodec_regWrite(TI3254_DAC_OSR_LSB_REG, 0x80);   // DOSR = 0x0080 = 128

                AudioCodec_regWrite(TI3254_CLK_NADC_REG, 0x80 | 0x01);      // NADC divider powered up, NADC = 1
                AudioCodec_regWrite(TI3254_CLK_MADC_REG, 0x80 | 0x08);      // MADC divider powered up, MADC = 8
                AudioCodec_regWrite(TI3254_ADC_OSR_REG, 0x80);       // AOSR = 128 ((Use with PRB_R1 to PRB_R6, ADC Filter Type A)

Trevor

0 Trevor Hsu over 6 years ago in reply to Trevor Hsu

Genius 4595 points

HI Clément,

Could you help to provide the 8KHz sampling rate setting for MCLK?

Thanks.

Trevor

0 Clément over 6 years ago in reply to Trevor Hsu

TI__Guru** 101460 points

Hi,

Here are the settings that I computed for 8kHz sampling frequency with MCLK as clock input (MCLK frequency is 1 MHz).

case 8000:  // Fs = 8kHz,  MCLK = input to PLL, MCLK = 1MHz (MCLKDivider = 48)
                 AudioCodec_pageSelect(TI3254_PAGE_0);

                 AudioCodec_regWrite(TI3254_CLK_MUX_REG, 0x13);       // PLL Clock is CODEC_CLKIN
                 AudioCodec_regWrite(TI3254_CLK_PLL_P_R_REG, 0x80 | 0x10 | 0x04);    // PLL is powered up, P=1, R=4
                 AudioCodec_regWrite(TI3254_CLK_PLL_J_REG, 0x020);     // J=32
                 AudioCodec_regWrite(TI3254_CLK_PLL_D_MSB_REG, 0x00); // D = 0000
                 AudioCodec_regWrite(TI3254_CLK_PLL_D_LSB_REG, 0x00); // D = 0000

                 AudioCodec_regWrite(TI3254_CLK_NDAC_REG, 0x80 | 0x19);      // NDAC divider powered up, NDAC = 25
                 AudioCodec_regWrite(TI3254_CLK_MDAC_REG, 0x80 | 0x05);      // MDAC divider powered up, MDAC = 5
                 AudioCodec_regWrite(TI3254_DAC_OSR_MSB_REG, 0x00);   // DOSR = 0x0080 = 128
                 AudioCodec_regWrite(TI3254_DAC_OSR_LSB_REG, 0x80);   // DOSR = 0x0080 = 128

                 AudioCodec_regWrite(TI3254_CLK_NADC_REG, 0x80 | 0x19);      // NADC divider powered up, NADC = 25
                 AudioCodec_regWrite(TI3254_CLK_MADC_REG, 0x80 | 0x05);      // MADC divider powered up, MADC = 5
                 AudioCodec_regWrite(TI3254_ADC_OSR_REG, 0x80);       // AOSR = 128 ((Use with PRB_R1 to PRB_R6, ADC Filter Type A)
                 break;

Regards,

0 Trevor Hsu over 6 years ago in reply to Clément

Genius 4595 points

Hi Clément,

Thanks for your help.

I made a summary for experimental results:

About 4KHz & 8KHz, I can hear the noise, I have checked the different input clock(MCLK & BCLK) .

Regarding 4KHz noise, , it always happens even if I unplug the Line-in cable, the noise looks like white noise.

Regarding 8KHz noise, it only happens when I stop playing music. The noise lasts about 2 seconds.

Do you have any suggestions to me??

Thanks.

Trevor

0 Clément over 6 years ago in reply to Trevor Hsu

TI__Guru** 101460 points

Hi,

Regarding your results, I guess the settings of the Codec are not perfect. This can be because the frequencies of the signals (BCLK, WCLK, MCLK) are not exactly as expected. Can you verify the actual frequency of BCLK, WCLK and MCLK using an oscilloscope?

Regards,

0 Trevor Hsu over 6 years ago in reply to Clément

Genius 4595 points

Hi Clément,

We need to take some time to prepare the oscilloscope, will update the result for you.

Thanks.

Trevor

0 Trevor Hsu over 6 years ago in reply to Trevor Hsu

Genius 4595 points

Hi Clément,

Update measurement results:

For 8KHz,

MCLK ~1.007MHz

BCLK ~8.034KHz

WCLK ~257KHz

For 4KHz,

MCLK ~1.007MHz

BCLK ~4.029KHz

WCLK ~129KHz

Do you have any thoughts? Do you think we need to open a new thread in "Audio Forum"?

Trevor.

0 Clément over 6 years ago in reply to Trevor Hsu

TI__Guru** 101460 points

Hi Trevor,

I assume you switch BCLK and WCLK frequencies (BCLK frequency is supposed to be higher than WCLK frequency). With that said, your frequencies look fine (at least you will not be able to get better accuracy). FYI: I tried to do the calculation with your actual frequencies but I got the same results.

Now, you can try to increase MCLK to see if this could help. I have prepared the following code for you:

case 4000:  // Fs = 4kHz,  MCLK = input to PLL, MCLK = 4.8MHz (MCLKDivider = 10)
                 AudioCodec_pageSelect(TI3254_PAGE_0);

                 AudioCodec_regWrite(TI3254_CLK_MUX_REG, 0x13);       // PLL Clock is CODEC_CLKIN
                 AudioCodec_regWrite(TI3254_CLK_PLL_P_R_REG, 0x80 | 0x30 | 0x02);    // PLL is powered up, P=3, R=2
                 AudioCodec_regWrite(TI3254_CLK_PLL_J_REG, 0x028);     // J=40
                 AudioCodec_regWrite(TI3254_CLK_PLL_D_MSB_REG, 0x00); // D = 0000
                 AudioCodec_regWrite(TI3254_CLK_PLL_D_LSB_REG, 0x00); // D = 0000

                 AudioCodec_regWrite(TI3254_CLK_NDAC_REG, 0x80 | 0x19);      // NDAC divider powered up, NDAC = 25
                 AudioCodec_regWrite(TI3254_CLK_MDAC_REG, 0x80 | 0x0A);      // MDAC divider powered up, MDAC = 10
                 AudioCodec_regWrite(TI3254_DAC_OSR_MSB_REG, 0x00);   // DOSR = 0x0080 = 128
                 AudioCodec_regWrite(TI3254_DAC_OSR_LSB_REG, 0x80);   // DOSR = 0x0080 = 128

                 AudioCodec_regWrite(TI3254_CLK_NADC_REG, 0x80 | 0x19);      // NADC divider powered up, NADC = 25
                 AudioCodec_regWrite(TI3254_CLK_MADC_REG, 0x80 | 0x0A);      // MADC divider powered up, MADC = 10
                 AudioCodec_regWrite(TI3254_ADC_OSR_REG, 0x80);       // AOSR = 128 ((Use with PRB_R1 to PRB_R6, ADC Filter Type A)
                 break;  


case 8000:  // Fs = 8kHz,  MCLK = input to PLL, MCLK = 4.8MHz (MCLKDivider = 10)
                 AudioCodec_pageSelect(TI3254_PAGE_0);

                 AudioCodec_regWrite(TI3254_CLK_MUX_REG, 0x13);       // PLL Clock is CODEC_CLKIN
                 AudioCodec_regWrite(TI3254_CLK_PLL_P_R_REG, 0x80 | 0x60 | 0x04);    // PLL is powered up, P=6, R=4
                 AudioCodec_regWrite(TI3254_CLK_PLL_J_REG, 0x028);     // J=40
                 AudioCodec_regWrite(TI3254_CLK_PLL_D_MSB_REG, 0x00); // D = 0000
                 AudioCodec_regWrite(TI3254_CLK_PLL_D_LSB_REG, 0x00); // D = 0000

                 AudioCodec_regWrite(TI3254_CLK_NDAC_REG, 0x80 | 0x19);      // NDAC divider powered up, NDAC = 25
                 AudioCodec_regWrite(TI3254_CLK_MDAC_REG, 0x80 | 0x05);      // MDAC divider powered up, MDAC = 5
                 AudioCodec_regWrite(TI3254_DAC_OSR_MSB_REG, 0x00);   // DOSR = 0x0080 = 128
                 AudioCodec_regWrite(TI3254_DAC_OSR_LSB_REG, 0x80);   // DOSR = 0x0080 = 128

                 AudioCodec_regWrite(TI3254_CLK_NADC_REG, 0x80 | 0x19);      // NADC divider powered up, NADC = 25
                 AudioCodec_regWrite(TI3254_CLK_MADC_REG, 0x80 | 0x05);      // MADC divider powered up, MADC = 5
                 AudioCodec_regWrite(TI3254_ADC_OSR_REG, 0x80);       // AOSR = 128 ((Use with PRB_R1 to PRB_R6, ADC Filter Type A)
                 break;

If this does not solve your problem then you should definitely ask Audio experts (by opening a new thread). Please don't forget to close the current thread (using the button "This Resolved my issue" on the most helpful messages), thanks.

Best regards,

0 Trevor Hsu over 6 years ago in reply to Clément

Genius 4595 points

Hi Clément,

Regarding your new setting, the result is the same with the 1MHz MCLK. But about 8K sample rate, I found that I used another mobile phone, the noise would disappear.

I will ask on "Audio forum" for 4KHz issue.

Thanks.

Trevor

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LAUNCHXL-CC26X2R1: i2secho example has white noise at 8K sample rate