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BT-MSPAUDSOURCE: I2S format and CLK/FSYNC direction

Part Number: BT-MSPAUDSOURCE

Hi Expert,

My Customer purchased BT-MSPAUDSOURCE board for BT-Headphone connection test using A2DP sink.
I got question regarding U12 and U5 connection below.

Q1) Signal format of AUD_IN:    I2S format ? and what bits (number of bits) is used ?
Q2) Direction of AUD_CLK and AUD_FSYN:  "U12 to U5" or "U5 to U12" ?

U12:TLV320ADC3101  U5:CC2560RVM

Best regards,
Saito

  • Hi Saito-san,

    Looking at the TLV codec setup code in the HAL.c of the sample code project used on the BT-MSPAUDSOURCE, it looks like AUD_IN is expected to be DSP mode, with 16bit data length. You can double-check these settings if you wish in the following section of the demo source code controlling the codec:

    /*    A2DP Source - Enable TLV320ADC3101 Playback       */
    /*    Configuration 2 -> PLL_CLKIN = BCLK               */
    /*                    -> Fs = 44.1KHz, BCLK = 3.528MHz  */
    /*                    -> Fs = 48KHz, BCLK = 3.840MHz    */
    /*                    -> Line-In                        */
    /*    Reference: ADC3101 Datasheet Page 40              */
    const unsigned char TxData_Line_In[] =
    {
      ///////////////// Initialization //////////////////
      // Px, P0              Switch to Page 0
      0x00, 0x00,
      // Software Reset Register
      // P0, R1, b0.         Reset = SW Reset - Internal Registers
      0x01, 0x01,
    
      ////////////// Digital Configuration //////////////
      // Px, P0              Switch to Page 0
      0x00, 0x00,
      // Clock Setting Register 1 - Multiplexers
      //    -> PLL_CLK = (PLL_CLKIN x R x J.D)/P
      //           - PLL_CLKIN = PCM_Fs x XX
      //    -> 84.672MHz = (3.528MHz  x 1 x 24.0)/1 --> For Fs = 44.1KHz
      //    -> 92.160MHz = (3.840MHz  x 1 x 24.0)/1 --> For Fs = 48KHz
      // P0, R4, b3-2.       PLL_CLKIN = BCLK (01)
      // P0, R4, b1-0.       CODEC_CLKIN = PLL_CLK (11)
      0x04, 0x07,
      // Clock Setting Register 2 - PLL P and R Values
      // P0, R5, b7.         PLL = Power Up (1)
      // P0, R5, b6-4.       PLL Divider P = 1 (001)
      // P0, R5, b3-0.       PLL Divider R = 1 (0001)
      0x05, 0x91,
      // Clock Setting Register 3 - PLL J Value
      // P0, R6, b5-0.       PLL Divider J = 24 (11000)
      0x06, 0x18,
      // Clock Setting Register 4 - PLL D Value
      // P0, R7, b5-0. (MSB) PLL Divider D = 0
      // P0, R8, b7-0. (LSB)
      0x07, 0x00,
      0x08, 0x00,
      // Clock Setting Register 18 - NDAC Values
      // P0, R18, b7.        NDAC = Power Up
      // P0, R18, b6-0.      NDAC = 3 (DAC_CLK = CODEC_CLKIN / NDAC)
      0x12, 0x83,
      // Clock Setting Register 19 - MDAC Values
      // P0, R19, b7.        MDAC = Power Up
      // P0, R19, b6-0.      MDAC = 8 (DAC_MOD_CLK = DAC_CLK / MDAC)
      0x13, 0x88,
      // DAC Setting Register 1 - AOSR Value
      //     -> ADC_Fs = CODEC_CLK_IN / (NDAC.MDAC.AOSR)
      //     -> 44.1KHz = 84.672MHz / (3.8.80)
      //     -> 48KHz = 92.160MHz / (3.8.80)
      //     -> MDAC * AOSR >= ResourceClass * 32
      //            - 8 * 80 >= 8 * 32 (256)
      //     -> 2.8MHz < AOSR x ADC_Fs < 6.2MHz
      //            - 80 * 44,100 = 3.528MHz
      //            - 80 * 48,000 = 3.840MHz
      //     -> AOSR must be a multiple of 8 (48KHz High-Performance)
      //     -> AOSR = 64, for Low-Power Mode
      //     -> AOSR = 128, for High-Performance Mode
      // P0, R20, b7-0       AOSR = 80 (ADC_Fs = ADC_MOD_CLK / AOSR)
      0x14, 0x50,
      // Audio Interface Setting Register 1 - Configuration
      // P0, R27, b7-6.      Interface Mode = DSP Mode (01)
      // P0, R27, b5-4.      Data Length = 16bits (00)
      // P0, R27, b3.        BCLK = Input (0)
      // P0, R27, b2.        WCLK = Input (0)
      0x1B, 0x40,
      // Audio Interface Setting Register 2 - Data Offset
      // P0, R28, b7-0.      Data Offset = 1
      0x1C, 0x01,
      // ADC Processing Block Set
      // Default PRB_P1
      // P0, R60, b4-0.     Processing Block: PRB_P1
      //    -> Filter A should be used for 48KHz High-Performance operation
      //    -> PRB_R1 - PRB_R6
      0x3D, 0x01,
    
      ////////////// Analog Configuration //////////////
      // Px, P0              Switch to Page 0
      0x00, 0x00,
      // Left ADC Volume Control Register
      // P1, R83, b6-0      Left ADC Volume = 0dB(000 0000)
      0x53, 0x00,
      // Right ADC Volume Control Register
      // P1, R84, b1-0      Right ADC Volume = 0dB(000 0000)
      0x54, 0x00,
      // Px, P1              Switch to Page 1
      0x00, 0x01,
      // MICBIAS Control Register
      // P1, R51, b6-5      MICBIAS1 = Power Down(00)
      // P1, R51, b4-3      MICBIAS2 = Power Down(00)
      0x33, 0x00,
      // Left ADC Input Selection for Left PGA Control Register
      // P1, R52, b1-0      LCH_SEL1 = IN1L(P) Single Ended 0dB (00)
      0x34, 0xFC,
      // Right ADC Input Selection for Right PGA Control Register
      // P1, R55, b1-0      LCH_SEL1 = IN1R(M) Single Ended 0dB (00)
      0x37, 0xFC,
      // Left Analog PGA Setting Register
      // P1, R59, b7        Left PGA is not muted (0)
      // P1, R59, b6-0      Left PGA Gain = +0dB (000 0000)
      0x3B, 0x00,
      // Right Analog PGA Setting Register
      // P1, R60, b7        Right PGA is not muted (0)
      // P1, R60, b6-0      Right PGA Gain = +0dB (000 0000)
      0x3C, 0x00,
    
      //////////////////// Power On ///////////////////
      // Px, P0              Switch to Page 0
      0x00, 0x00,
      // ADC Digital Register
      // P0, R81, b7.        Left Channel ADC Power = Power Up (1)
      // P0, R81, b6.        Right Channel ADC Power = Power Up (1)
      // P0, R81, b1-0.      Soft-Step Control = Enabled, 1 Step/2*Fs (01)
      0x51, 0xC1,
      // ADC Fine Volume Control Register
      // P0, R82, b7.        Left Channel Mute = No (0)
      // P0, R82, b6-4.      Left ADC Channel Gain =0dB (000)
      // P0, R82, b3.        Right Channel Mute = No (0)
      // P0, R82, b2-0.      Right ADC Channel Gain =0dB (000)
      0x52, 0x00
    };

    As for the direction of AUD_CLK and AUD_FSYN, it should be from the CC256x device to the TLV, so from U5 to U12.

    Let me know if you need more clarification or have further questions on the I2S setup on this demo.

    Regards,

    Michael

  • Hello Michael,

    You mentioned that
    >the I2S setup on this demo

    An then, Customer got the waveform. 20210421_waveform.zip

    Q1) However,  it is not I2S format. just like TDM format as shown in below. Is that correct ?


    Q2) If this is not I2S format on BT-MSPAUDSOURCE board, is it possible to change to I2S format ? and please tell us how to change to I2S format.

       CC2564C datasheet (SWRS199B) says:
            6.4.3.2 I2S
            When the codec interface is configured to support the I2S protocol, these settings are recommended:
              • Bidirectional, full-duplex interface
              • Two time slots per frame: time slot 0 for the left channel audio data; and time slot 1 for the right channel audio data
              • The length of each time slot is configurable up to 40 serial clock cycles, and the length of the frame is configurable up to 80 serial clock cycles

    Thank you for your help.
    Best regards,
    Saito

  • Hi Saito-san,

    As I mentioned in my previous post, the audio interface is configured for DSP mode operation, not I2S. A detailed description of this mode can be found in the codec datasheet, section 10.3: https://www.ti.com/lit/ds/symlink/tlv320adc3101.pdf

    If you wanted to change it to I2S mode, there are two main things you need to do:

    1. You will need to change the TLV codec config, in HAL_ConfigureCodec of HAL.c, in order to enable I2S instead of DSP mode. This is something you will need to perform on your own, or ask the appropriate codec group for help if needed - I do not have expertise on that part.

    2. You will need to set the CC2564 to output I2S formatted PCM instead of DSP format. To do this, you will need to modify the ReconfigureA3DPStream() function of A3DPDemo_SRC.c, specifically the VS_PCM_Codec_Config(). There is documentation on that function itself in BTVS.c, and it will need to match the codec settings.

    Regards,

    Michael