Tool/software:
How much jitter does CC2500's bit synchronization algorithm have?
Used under the conditions of data rate 250kbps and modulation method FSK.
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Tool/software:
How much jitter does CC2500's bit synchronization algorithm have?
Used under the conditions of data rate 250kbps and modulation method FSK.
Hello,
Are you asking for how much jitter the clock recovery process would introduce? What are you trying to do or what error are you seeing? This parameter isn't specified and I'm not sure that it's meaningful or feasible to measure. Any clock recovered from the incoming signal would be synced to the CC2500's crystal oscillator.
Hello,
Thank you for your answer.
We are currently in the process of selecting the device to use.
I would like to know the jitter when used with the following parameters.
Is the amount of jitter in the recovered clock related to preamble length or data rate?
data rate:250kbps
modulation method:FSK
Regards,
toshiyuki takahashi
Hello,
I'm still not sure I understand the issue you're trying to resolve. Let me try to restate to make sure I understand the details:
For the received signal there will be a certain preamble and sync word. For 250kbps the data sheet requirement for preamble is 4 bytes and for sync word is 4 bytes (see section 15 packet handling hardware support). During reception the bit stream is synchronized by using the preamble and the bytes are synchronized using the sync word (see 14.2 and 14.3 from the data sheet). From here, incoming data would be written to the FIFO to then be accessed by the serial or SPI output. So any clock and data recovery would be completely internal to the device. I don't even think it's possible to specify what the jitter is in this case.
Alternatively you could be using asynchronous mode where the received signal is output directly to a pin but in this case packet handling isn't involved and so bit synchronization is not involved. All the handling would need to be done by your MCU.
Thanks,
Jake