CC1175 Frequency Synthesizer bandwidth can be adjusted over a modest range (101.6 - 170.8 KHz) via settings in the FS_DIG0 register according to the User's Guide.
I'm wondering if the bandwidth can be made even lower by changing external components? The datasheet mentions "external loop filter components" for the pins: LPF0 and LPF1, however the application circuit diagram and reference design have only a single capacitor connected between these pins, and neither the datasheet nor user's guide provide any guidance about alternate circuit topology which might be used to modify loop bandwidth.
Is any guidance available about alternate circuit topology or component values which could be used in conjunction with LPF0/LPF1 pins to modify (lower) the Frequency Synthesizer loop bandwidth? My application would benefit from much lower bandwidth.
Thanks!