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RTOS/CC2650: Unable to use Cache as RAM on RTOS V 2.11

Part Number: CC2650
Other Parts Discussed in Thread: SYSBIOS

Tool/software: TI-RTOS

Hello All,

Environment :CC26504XS custom board, IAR Workbench version - 7.40.2.8570, TIMAC - 1.5.2, TI RTOS - V 2.11.01.09. TI RTOS V 2.11 is selected as it supports TI MAC.

On TI RTOS V2.11, I am unable to use Cache as RAM, however the same is working fine on RTOS V2.16.

I have followed the steps mentioned in the below link:

http://dev.ti.com/tirex/content/simplelink_cc2640r2_sdk_1_50_00_58/docs/blestack/ble_user_guide/html/cc2640/memory_management.html#using-the-cache-as-ram

On RTOS V2.11, ccfg.c DEFAULT_CCFG_SIZE_AND_DIS_FLAGS is defined as below without GPRAM flags, 

#define DEFAULT_CCFG_SIZE_AND_DIS_FLAGS ( \
( ((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG << CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_S )) | ~CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_M ) & \
( ((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS << CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S )) | ~CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M ) & \
( ((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING << CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_S )) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_M ) & \
( ((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR << CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_S )) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) )

The flags CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S and CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M are not defined in hw_ccfg.h of V 2.11 hence I modified the DEFAULT_CCFG_SIZE_AND_DIS_FLAGS as below by defining CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S, CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M as the same values that of startup/ccfg.c of RTOS V 2.16.

#define DEFAULT_CCFG_SIZE_AND_DIS_FLAGS ( \
( ((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG << CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_S )) | ~CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_M ) & \
( ((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS << CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S )) | ~CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M ) & \
( ((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM << CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S )) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M ) & \
( ((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING << CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_S )) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_M ) & \
( ((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR << CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_S )) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) )

compiler/linker files are also correctly defined. 

Code compiles, links and loads. If i check the GPRAM memory its contents are "-- -- --" no data is available in GPRAM.

Please suggest if there are specific settings needs to be performed for RTOS V 2.11.

Best regards

Naveen

  • Which SDK and version are you using?
  • Hi Edvard,

    I am using TI-RTOS 2.11.01.09, I am not sure if this is what you mean by SDK Version.

    When we started our development 2 years back, it was decided to use this version and this was the latest RTOS version with TI MAC that was available at that point of time. 

    Best Regards

    Naveen

  • Hi Naveen,

    If I understand you correct, you have defined both missing defines, CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S and CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M, just as its defined in hw_ccfg.h of V 2.16, and you have defined SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM to be zero in your ccfg.

    If so, did you follow rest of the steps, such as setting cache in retention?
  • Hi Edvard,

    Your understanding is correct, in addition to defining CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S, CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M and SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM to 0 I followed all the steps required to use the Cache as RAM.
    The same steps works correctly with RTOS V 2.16.

    Another observation is Power constraints have different values defined between V 2.11 and V 2.16, I have not changed the constraint values of V 2.11 and used as is.

    V 2.16
    /* Constraints */
    #define PowerCC26XX_SB_VIMS_CACHE_RETAIN 0
    #define PowerCC26XX_SD_DISALLOW 1
    #define PowerCC26XX_SB_DISALLOW 2
    #define PowerCC26XX_IDLE_PD_DISALLOW 3
    #define PowerCC26XX_NEED_FLASH_IN_IDLE 4
    #define PowerCC26XX_NUMCONSTRAINTS 5

    V 2.11
    /* Constraint */
    enum ti_sysbios_family_arm_cc26xx_Power_Constraint {
    ti_sysbios_family_arm_cc26xx_Power_SB_VIMS_CACHE_RETAIN = 0x1,
    ti_sysbios_family_arm_cc26xx_Power_SD_DISALLOW = 0x2,
    ti_sysbios_family_arm_cc26xx_Power_SB_DISALLOW = 0x4,
    ti_sysbios_family_arm_cc26xx_Power_IDLE_PD_DISALLOW = 0x8,
    ti_sysbios_family_arm_cc26xx_Power_NEED_FLASH_IN_IDLE = 0x10,
    ti_sysbios_family_arm_cc26xx_Power_NUMCONSTRAINTS = 5
    };

    Best regards
    Naveen
  • Hi Edvard and other Gurus of the forum,

    Any thoughts on this issue. Please help.

    Regards

    Naveen

  • Hi Naveen,

    It is hard to say whether this is well supported with the TI-RTOS version you are using, since you are using an old version of TI-RTOS. I suggest to follow the guide you linked to in your post, and not to change the Constraint values.

    If that doesn't work, then it is a great possibility the TI-RTOS version you are using is not able to support Cache as RAM. If so, then I would suggest for you to consider upgrading the TI-RTOS version you are using.