Help, I can't seem to get TRF7960 SPI working. Requesting a schematic review.

Phil -

i won't claim that i am smarter than anyone - but here are my comments about your diagram and notes

1. EN and EN2 cannot come up at the same time - this is correct. EN2 can be tied low and then EN tied high, with a pulldown to ground as this pin needs to see low to high transition. Not using GPIO on these lines limits your low power mode options, though. You may also notice a small TX (200mV or so) spike on power up because of the automatic setting of the regulators when using the part this way.

2. You could use VDD_X for the VDD_I/O input - this would save you a line on your connector.

3. I/O_1 and I/O_2 cannot be tied to +5V is the I/O voltage is set for 3.3VDC - these are also I/O lines and should be at same voltage levels as the other I/O. You can also tie them directly to VDD_X or the 3.3V supply you have already and save yourself R1 and R4 parts.

4. the MCU clock does not have to come from the TRF. this is OK. we do this too with other MSP430s, Cortex M3, ARM7/8 and DSP parts when implementing the TRF ckt with those devices.

5. connection J1...you could use MSP430? (you don't really want to stay with an 8051 core do you? :)

6. for the register read back, you do know that you need to switch the clock polarity with the TRF796x devices, correct? for the MOSI line CPHA = 0, for the MISO line CPHA = 1...see figure 5-17 on page 33 http://www.ti.com/lit/ds/symlink/trf7960a.pdf

7. on the antenna tuning, i know that you said you copied our coil, but just in case, if you have the ability to double check on network analyzer what you have created this would be a good thing to do

hope that helps you out.

Thank you for getting back to me.  A few new questions:

My prototypes contain the TRF7960 not the A version.  I asume all this applies to all TRF796x?

My application is ISO 15693 only and I see you have TRF7962A on deck for that.  I have to spin the PCB so what is the best strategy to bring on a 100/month product on-line in 2012Q4?  Should I avoid the 7960/7961 and start the product with the 7960A then do a cost reduction with a transisiton to 7962A next year?  Other?

I have also have inserted a few questions into your earlier response below.

Thanks again.

Phil

1. EN and EN2 cannot come up at the same time - this is correct. EN2 can be tied low and then EN tied high, with a pulldown to ground as this pin needs to see low to high transition. Not using GPIO on these lines limits your low power mode options, though. You may also notice a small TX (200mV or so) spike on power up because of the automatic setting of the regulators when using the part this way.

The application is in an AC powered computer peripheral so I don't need to minimize power consumption which isn't much with the transimitter turned off.
I'm not sure how to tie EN high with a pulldown to ground?  Could I tie EN and EN2 to +5V (or should it be VDD_IO?)  through 10K pullups with a capacitor to ground to on EN get the necessary delay in low>high transistion at start-up?

What are the timing & signal rise time requirements?

Is it unwise not to conrtol EN vi GPIO, i.e. is it possible for the ASIC to hang requiring a HLH pulse on EN to reset it?

2. You could use VDD_X for the VDD_I/O input - this would save you a line on your connector.

3. I/O_1 and I/O_2 cannot be tied to +5V is the I/O voltage is set for 3.3VDC - these are also I/O lines and should be at same voltage levels as the other I/O. You can also tie them directly to VDD_X or the 3.3V supply you have already and save yourself R1 and R4 parts.

Do you think I have damaged the part given that these were tied to +5 through a 10K resistor which should have limited the current in to the ESD protection diodes to ~100uA?

4. the MCU clock does not have to come from the TRF. this is OK. we do this too with other MSP430s, Cortex M3, ARM7/8 and DSP parts when implementing the TRF ckt with those devices.

5. connection J1...you could use MSP430? (you don't really want to stay with an 8051 core do you? :)

I wouldn't mind doing an MSP430 or Stellaris design but unfortunately I have a legacy of 8051 based products that I am updating and dont' have time to port over to a new MCU.  Although can you identify form me the the right low cost JTAG/compiler PN to use to program the EVM?

6. for the register read back, you do know that you need to switch the clock polarity with the TRF796x devices, correct? for the MOSI line CPHA = 0, for the MISO line CPHA = 1...see figure 5-17 on page 33 http://www.ti.com/lit/ds/symlink/trf7960a.pdf

Yes, I have that working as I can readd back what I see in the SPI trace.

7. on the antenna tuning, i know that you said you copied our coil, but just in case, if you have the ability to double check on network analyzer what you have created this would be a good thing to do.

I do not have a network analyzer.  I plan to worry abou that afer I know I can control the chip.  An untuned antenna should not prevent SPI communication with the chip right?

Can you recommend an organization I could contrat to tune it?

hope that helps you out.