SMARTRFTM-STUDIO: CC1100

Oleg UGR

Part Number: SMARTRFTM-STUDIO
Other Parts Discussed in Thread: CC1100, CC1150, CC1101

Hello,

I use RF Studio 7 to set the registers for lower data rate and RX BW. I have working setting for a long time for CC1100 RF chip, 250kbps, 540KHz, MSK, 433.92MHz.
I noticed kind of not accurate tool performance, when basing on one typical setting and changing the data rate and BW will cause only MDMCFG4 to be changed. But when basing on other typical setting and changing the parameters will cause additional to MDMCFG4 registers changes like: FSCTRL1, FOCCFG, BSCFG, AGCCTRL2, AGCCTRL1, AGCCTRL0, FREND1, FSCAL3.
I looked on CC1100 datasheet to validate those changes, but still doesn't make sense since if reducing data rate why AGC setting should be reduced, like LNA gain is reduced from maximum settings. And don't understand why other registers are affected as well ?
Both options to set the tool don't lead to desire performance, changing only MDMCFG4 showed worse performance for 125kb/270KHz than 250kbps/540KHz. And when changed other registers as well according to the tool, still don't see much improvement.
So, what's the best method to work with the tool? to use ccdebuger?

over 6 years ago

0 TER over 6 years ago

TI__Guru**** 317180 points

SmartRF Studio does not recalculate all setting if you change one or two parameters.

The tool calculate the settings for frequency, datarate, deviation and RX BW but if you change one of these parameters you have to evaluate if some of the other registers also have to be changed. Therefore always start from the predefined setting that is closest to the one you need (typically the RX BW) and change this based on your needs with the support from the datasheet.

0 Oleg UGR over 6 years ago in reply to TER

Prodigy 45 points

One specific concern I have is about dealing with frequency offsets between a CC1150 transmitter and CC1100 receiver when using MSK. I know that there is Frequency Offset Control provided by the FOCCFG register & I have played around with these settings experimentally and have a pretty good idea of how the FOC_LIMIT setting effects ability to receive vs. frequency offset. So, here are my questions:

1) When I'm opening up FOC_LIMIT to 3(11)=[+/- BWchan/2] or to 2(10) [BWchan/4] - seems I have reasonable traffic and sensitivity levels, but when its OFF (00) or BW/8 (01) - I don't receive any data @31.25 kbps. I see also that BW/8 setting works fine @250 kbps. So, why it's related to different data rates? Is there any downside to this in terms of sensitivity or acquisition time or anything else? It seems like there must be a tradeoff somewhere – so I just want to know what the tradeoff is.

2) I have not played with the FOC_PRE_K setting – what are the issues with changing that from whatever default setting is used now? I’ve got it at 2(10)=3k loop gain now.

0 TER over 6 years ago in reply to Oleg UGR

TI__Guru**** 317180 points

I'm not familiar with the frequency offset tracking on CC1101 so I have to check with someone after Easter (the persons in question have Easter vacation).

But looking at the predefined settings in SmartRF Studio it looks like the FOC_LIMIT should be low for high datarates. Both for 38.4 kbps and 250 kbps we have predefined settings I would recommend you to follow.

Does anything work as expected if you follow the settings given by SmartRF Studio?

0 Oleg UGR over 6 years ago in reply to TER

Prodigy 45 points

Thanks for your reply!
Suggested by RF Studio FOCCFG settings work at 31.25kbps, not as expected, there are only around 3db of improvement, instead of 9db in sensitivity level (according to datasheet), comparing to 250kbps.
In general, I would like to have better understanding of FOCCFG mechanism and why its necessary to turn on the frequency offset compensation when the data rate is low (31.25kbps).
Could you check these details?

0 Sverre over 6 years ago in reply to Oleg UGR

TI__Mastermind 39860 points

Please provide the register settings you are using and a short summary of the PHY parameters (e.g. data rate, deviation, RX filter BW). I suspect there is an issue with the settings you are using. One thing: you use MSK for 250 kbps. For 31.25 kbps you should use 2GFSK. Not clear from your post if this is the case.

0 Oleg UGR over 6 years ago in reply to Sverre

Prodigy 45 points

CC1100_31_25_last.html

<html><head>
<style>
body {background-color:#dde;}
caption {font-weight:bold; font-size:16px;margin-left:30px}
th { text-align:left; background-color:#f00; color:#fff}
table { background-color: #eec; font-size:9px;margin:10px}
</style>
</head>
<body><table border=1 cellpadding=5 cellspacing=0>
<caption>CC1100 registers</caption>
<tr><th>Name</th><th>Address</th><th>Value</th>
<th>Description</th></tr><tr><td>IOCFG2<td>0x0000</td><td>0x6F</td><td>GDO2 Output Pin Configuration</td></tr>
<tr><td>IOCFG1<td>0x0001</td><td>0x2E</td><td>GDO1 Output Pin Configuration</td></tr>
<tr><td>IOCFG0<td>0x0002</td><td>0x07</td><td>GDO0 Output Pin Configuration</td></tr>
<tr><td>FIFOTHR<td>0x0003</td><td>0x04</td><td>RX FIFO and TX FIFO Thresholds</td></tr>
<tr><td>SYNC1<td>0x0004</td><td>0xD3</td><td>Sync Word, High Byte</td></tr>
<tr><td>SYNC0<td>0x0005</td><td>0x91</td><td>Sync Word, Low Byte</td></tr>
<tr><td>PKTLEN<td>0x0006</td><td>0xFF</td><td>Packet Length</td></tr>
<tr><td>PKTCTRL1<td>0x0007</td><td>0x0F</td><td>Packet Automation Control</td></tr>
<tr><td>PKTCTRL0<td>0x0008</td><td>0x05</td><td>Packet Automation Control</td></tr>
<tr><td>ADDR<td>0x0009</td><td>0x00</td><td>Device Address</td></tr>
<tr><td>CHANNR<td>0x000A</td><td>0x00</td><td>Channel Number</td></tr>
<tr><td>FSCTRL1<td>0x000B</td><td>0x0A</td><td>Frequency Synthesizer Control</td></tr>
<tr><td>FSCTRL0<td>0x000C</td><td>0x00</td><td>Frequency Synthesizer Control</td></tr>
<tr><td>FREQ2<td>0x000D</td><td>0x10</td><td>Frequency Control Word, High Byte</td></tr>
<tr><td>FREQ1<td>0x000E</td><td>0xB0</td><td>Frequency Control Word, Middle Byte</td></tr>
<tr><td>FREQ0<td>0x000F</td><td>0x71</td><td>Frequency Control Word, Low Byte</td></tr>
<tr><td>MDMCFG4<td>0x0010</td><td>0xEA</td><td>Modem Configuration</td></tr>
<tr><td>MDMCFG3<td>0x0011</td><td>0x3B</td><td>Modem Configuration</td></tr>
<tr><td>MDMCFG2<td>0x0012</td><td>0x73</td><td>Modem Configuration</td></tr>
<tr><td>MDMCFG1<td>0x0013</td><td>0x02</td><td>Modem Configuration</td></tr>
<tr><td>MDMCFG0<td>0x0014</td><td>0xF8</td><td>Modem Configuration</td></tr>
<tr><td>DEVIATN<td>0x0015</td><td>0x00</td><td>Modem Deviation Setting</td></tr>
<tr><td>MCSM2<td>0x0016</td><td>0x07</td><td>Main Radio Control State Machine Configuration</td></tr>
<tr><td>MCSM1<td>0x0017</td><td>0x0F</td><td>Main Radio Control State Machine Configuration</td></tr>
<tr><td>MCSM0<td>0x0018</td><td>0x18</td><td>Main Radio Control State Machine Configuration</td></tr>
<tr><td>FOCCFG<td>0x0019</td><td>0x16</td><td>Frequency Offset Compensation Configuration</td></tr>
<tr><td>BSCFG<td>0x001A</td><td>0x6C</td><td>Bit Synchronization Configuration</td></tr>
<tr><td>AGCCTRL2<td>0x001B</td><td>0x07</td><td>AGC Control</td></tr>
<tr><td>AGCCTRL1<td>0x001C</td><td>0x49</td><td>AGC Control</td></tr>
<tr><td>AGCCTRL0<td>0x001D</td><td>0x32</td><td>AGC Control</td></tr>
<tr><td>WOREVT1<td>0x001E</td><td>0x87</td><td>High Byte Event0 Timeout</td></tr>
<tr><td>WOREVT0<td>0x001F</td><td>0x6B</td><td>Low Byte Event0 Timeout</td></tr>
<tr><td>WORCTRL<td>0x0020</td><td>0xF8</td><td>Wake On Radio Control</td></tr>
<tr><td>FREND1<td>0x0021</td><td>0x56</td><td>Front End RX Configuration</td></tr>
<tr><td>FREND0<td>0x0022</td><td>0x10</td><td>Front End TX Configuration</td></tr>
<tr><td>FSCAL3<td>0x0023</td><td>0xE9</td><td>Frequency Synthesizer Calibration</td></tr>
<tr><td>FSCAL2<td>0x0024</td><td>0x2A</td><td>Frequency Synthesizer Calibration</td></tr>
<tr><td>FSCAL1<td>0x0025</td><td>0x00</td><td>Frequency Synthesizer Calibration</td></tr>
<tr><td>FSCAL0<td>0x0026</td><td>0x1F</td><td>Frequency Synthesizer Calibration</td></tr>
<tr><td>RCCTRL1<td>0x0027</td><td>0x41</td><td>RC Oscillator Configuration</td></tr>
<tr><td>RCCTRL0<td>0x0028</td><td>0x00</td><td>RC Oscillator Configuration</td></tr>
<tr><td>FSTEST<td>0x0029</td><td>0x59</td><td>Frequency Synthesizer Calibration Control</td></tr>
<tr><td>PTEST<td>0x002A</td><td>0x7F</td><td>Production Test</td></tr>
<tr><td>AGCTEST<td>0x002B</td><td>0x3F</td><td>AGC Test</td></tr>
<tr><td>TEST2<td>0x002C</td><td>0x81</td><td>Various Test Settings</td></tr>
<tr><td>TEST1<td>0x002D</td><td>0x35</td><td>Various Test Settings</td></tr>
<tr><td>TEST0<td>0x002E</td><td>0x09</td><td>Various Test Settings</td></tr>
<tr><td>PARTNUM<td>0x0030</td><td>0x00</td><td>Chip ID</td></tr>
<tr><td>VERSION<td>0x0031</td><td>0x04</td><td>Chip ID</td></tr>
<tr><td>FREQEST<td>0x0032</td><td>0x00</td><td>Frequency Offset Estimate from Demodulator</td></tr>
<tr><td>LQI<td>0x0033</td><td>0x00</td><td>Demodulator Estimate for Link Quality</td></tr>
<tr><td>RSSI<td>0x0034</td><td>0x00</td><td>Received Signal Strength Indication</td></tr>
<tr><td>MARCSTATE<td>0x0035</td><td>0x00</td><td>Main Radio Control State Machine State</td></tr>
<tr><td>WORTIME1<td>0x0036</td><td>0x00</td><td>High Byte of WOR Time</td></tr>
<tr><td>WORTIME0<td>0x0037</td><td>0x00</td><td>Low Byte of WOR Time</td></tr>
<tr><td>PKTSTATUS<td>0x0038</td><td>0x00</td><td>Current GDOx Status and Packet Status</td></tr>
<tr><td>VCO_VC_DAC<td>0x0039</td><td>0x00</td><td>Current Setting from PLL Calibration Module</td></tr>
<tr><td>TXBYTES<td>0x003A</td><td>0x00</td><td>Underflow and Number of Bytes</td></tr>
<tr><td>RXBYTES<td>0x003B</td><td>0x00</td><td>Overflow and Number of Bytes</td></tr>
<tr><td>RCCTRL1_STATUS<td>0x003C</td><td>0x00</td><td>Last RC Oscillator Calibration Result</td></tr>
<tr><td>RCCTRL0_STATUS<td>0x003D</td><td>0x00</td><td>Last RC Oscillator Calibration Result</td></tr>
</table>
</body><html>

CC1150_UHF_settings.txt data-mode="text" data-theme="light" style="height:922px;min-width:1230px;margin:0px;" data-gutter="true"> DB 0x06 ; IOCFG0 - Temp sensor off, GDO0 - assert on sync, then desert on Tx complete ; IOCFG1 - Drive strength low, GDO1_Inv off, GDO1 - High Z ; SYNC1 - Sync word high byte ; FIFOTHR - Don't care not in use ; PKTLEN - Don't care not in use ; SYNC0 - Sync word low byte ; PKTCNTL0 - Whitening off, Normal mode, CC2400 support off, CRC enabled, Variable packet length ; PKTCNTL1 - CC1100 only ; CHANNR - Channel number ; ADDR - destinaation address ; FSCNTL0 - CC1100 only ; FSCNTL1 - CC1100 only ; FREQ1 - Frequency control ; FREQ2 - Frequency control ;0x0D MDMCFG4 - Modulation control exponent - 13 ; FREQ0 - Frequency control ; MDMCFG2 - Modulation control - MSK, Manchester off, sync mode 16 bits ; MDMCFG3 - Modulation control Mantissa - 59 ; MDMCFG0 - Modulation control - CH spacing mantissa = 248 ; MDMCFG1 - Modulation control - FEC off, 4 preamble bytes, CH spacing exponet= 2 ; MCSM2 - CC1100 only ;DEVIATN - Mantissa and exponent of deviation setting ; MCSM0 - Manual cal, PO_timeout = fastest ; MCSM1 - Tx off mode idle ; BSCFG - CC1100 only ; FOCCFG - CC1100 only ; AGCCNTL1 - CC1100 only ; AGCCNTL2 - CC1100 only ; WOREVT1 - CC1100 only ; AGCCNTL0 - CC1100 only ; WORCNTL - CC1100 only ; WOREVT0 - CC1100 only ; FREND0 - Tx curretn divider, and PA-Table index = 0 ; FREND1 - CC1100 only

Please see attached files with CC1100 (Rx side) and CC1150 (Tx side) registers settings.

PHY parameters:
Freq: 433.92MHz, data rate: 31.25kbps, MSK, RX BW: 68KHz, crystal: 26MHz (15ppm), Tx power: +10dbm
BTW, why can't I use MSK for 31.25kb?

0 Sverre over 6 years ago in reply to Oleg UGR

TI__Mastermind 39860 points

MSK works fine for 250 and 500 kbps, but for lower data rates we recommend 2-GFSK modulation. You can emulate MSK by using a modulation index of 0.5. That is, deviation = symbol rate/4. The register settings I would have used as a starting point are attached. The RF related settings should be ok, but you can change packet handling features as you see fit.

CC1100_31kbps_GFSK.html

<html><head>
<style>
body {background-color:#dde;}
caption {font-weight:bold; font-size:16px;margin-left:30px}
th { text-align:left; background-color:#f00; color:#fff}
table { background-color: #eec; font-size:9px;margin:10px}
</style>
</head>
<body><table border=1 cellpadding=5 cellspacing=0>
<caption>CC1100 registers</caption>
<tr><th>Name</th><th>Address</th><th>Value</th>
<th>Description</th></tr><tr><td>IOCFG2<td>0x0000</td><td>0x29</td><td>GDO2 Output Pin Configuration</td></tr>
<tr><td>IOCFG1<td>0x0001</td><td>0x2E</td><td>GDO1 Output Pin Configuration</td></tr>
<tr><td>IOCFG0<td>0x0002</td><td>0x06</td><td>GDO0 Output Pin Configuration</td></tr>
<tr><td>FIFOTHR<td>0x0003</td><td>0x07</td><td>RX FIFO and TX FIFO Thresholds</td></tr>
<tr><td>SYNC1<td>0x0004</td><td>0xD3</td><td>Sync Word, High Byte</td></tr>
<tr><td>SYNC0<td>0x0005</td><td>0x91</td><td>Sync Word, Low Byte</td></tr>
<tr><td>PKTLEN<td>0x0006</td><td>0xFF</td><td>Packet Length</td></tr>
<tr><td>PKTCTRL1<td>0x0007</td><td>0x04</td><td>Packet Automation Control</td></tr>
<tr><td>PKTCTRL0<td>0x0008</td><td>0x05</td><td>Packet Automation Control</td></tr>
<tr><td>ADDR<td>0x0009</td><td>0x00</td><td>Device Address</td></tr>
<tr><td>CHANNR<td>0x000A</td><td>0x00</td><td>Channel Number</td></tr>
<tr><td>FSCTRL1<td>0x000B</td><td>0x06</td><td>Frequency Synthesizer Control</td></tr>
<tr><td>FSCTRL0<td>0x000C</td><td>0x00</td><td>Frequency Synthesizer Control</td></tr>
<tr><td>FREQ2<td>0x000D</td><td>0x10</td><td>Frequency Control Word, High Byte</td></tr>
<tr><td>FREQ1<td>0x000E</td><td>0xB0</td><td>Frequency Control Word, Middle Byte</td></tr>
<tr><td>FREQ0<td>0x000F</td><td>0x71</td><td>Frequency Control Word, Low Byte</td></tr>
<tr><td>MDMCFG4<td>0x0010</td><td>0xEA</td><td>Modem Configuration</td></tr>
<tr><td>MDMCFG3<td>0x0011</td><td>0x13</td><td>Modem Configuration</td></tr>
<tr><td>MDMCFG2<td>0x0012</td><td>0x13</td><td>Modem Configuration</td></tr>
<tr><td>MDMCFG1<td>0x0013</td><td>0x22</td><td>Modem Configuration</td></tr>
<tr><td>MDMCFG0<td>0x0014</td><td>0xF8</td><td>Modem Configuration</td></tr>
<tr><td>DEVIATN<td>0x0015</td><td>0x22</td><td>Modem Deviation Setting</td></tr>
<tr><td>MCSM2<td>0x0016</td><td>0x07</td><td>Main Radio Control State Machine Configuration</td></tr>
<tr><td>MCSM1<td>0x0017</td><td>0x30</td><td>Main Radio Control State Machine Configuration</td></tr>
<tr><td>MCSM0<td>0x0018</td><td>0x18</td><td>Main Radio Control State Machine Configuration</td></tr>
<tr><td>FOCCFG<td>0x0019</td><td>0x16</td><td>Frequency Offset Compensation Configuration</td></tr>
<tr><td>BSCFG<td>0x001A</td><td>0x6C</td><td>Bit Synchronization Configuration</td></tr>
<tr><td>AGCCTRL2<td>0x001B</td><td>0x43</td><td>AGC Control</td></tr>
<tr><td>AGCCTRL1<td>0x001C</td><td>0x40</td><td>AGC Control</td></tr>
<tr><td>AGCCTRL0<td>0x001D</td><td>0x91</td><td>AGC Control</td></tr>
<tr><td>WOREVT1<td>0x001E</td><td>0x87</td><td>High Byte Event0 Timeout</td></tr>
<tr><td>WOREVT0<td>0x001F</td><td>0x6B</td><td>Low Byte Event0 Timeout</td></tr>
<tr><td>WORCTRL<td>0x0020</td><td>0xF8</td><td>Wake On Radio Control</td></tr>
<tr><td>FREND1<td>0x0021</td><td>0x56</td><td>Front End RX Configuration</td></tr>
<tr><td>FREND0<td>0x0022</td><td>0x10</td><td>Front End TX Configuration</td></tr>
<tr><td>FSCAL3<td>0x0023</td><td>0xE9</td><td>Frequency Synthesizer Calibration</td></tr>
<tr><td>FSCAL2<td>0x0024</td><td>0x2A</td><td>Frequency Synthesizer Calibration</td></tr>
<tr><td>FSCAL1<td>0x0025</td><td>0x00</td><td>Frequency Synthesizer Calibration</td></tr>
<tr><td>FSCAL0<td>0x0026</td><td>0x1F</td><td>Frequency Synthesizer Calibration</td></tr>
<tr><td>RCCTRL1<td>0x0027</td><td>0x41</td><td>RC Oscillator Configuration</td></tr>
<tr><td>RCCTRL0<td>0x0028</td><td>0x00</td><td>RC Oscillator Configuration</td></tr>
<tr><td>FSTEST<td>0x0029</td><td>0x59</td><td>Frequency Synthesizer Calibration Control</td></tr>
<tr><td>PTEST<td>0x002A</td><td>0x7F</td><td>Production Test</td></tr>
<tr><td>AGCTEST<td>0x002B</td><td>0x3F</td><td>AGC Test</td></tr>
<tr><td>TEST2<td>0x002C</td><td>0x81</td><td>Various Test Settings</td></tr>
<tr><td>TEST1<td>0x002D</td><td>0x35</td><td>Various Test Settings</td></tr>
<tr><td>TEST0<td>0x002E</td><td>0x09</td><td>Various Test Settings</td></tr>
<tr><td>PARTNUM<td>0x0030</td><td>0x00</td><td>Chip ID</td></tr>
<tr><td>VERSION<td>0x0031</td><td>0x04</td><td>Chip ID</td></tr>
<tr><td>FREQEST<td>0x0032</td><td>0x00</td><td>Frequency Offset Estimate from Demodulator</td></tr>
<tr><td>LQI<td>0x0033</td><td>0x00</td><td>Demodulator Estimate for Link Quality</td></tr>
<tr><td>RSSI<td>0x0034</td><td>0x00</td><td>Received Signal Strength Indication</td></tr>
<tr><td>MARCSTATE<td>0x0035</td><td>0x00</td><td>Main Radio Control State Machine State</td></tr>
<tr><td>WORTIME1<td>0x0036</td><td>0x00</td><td>High Byte of WOR Time</td></tr>
<tr><td>WORTIME0<td>0x0037</td><td>0x00</td><td>Low Byte of WOR Time</td></tr>
<tr><td>PKTSTATUS<td>0x0038</td><td>0x00</td><td>Current GDOx Status and Packet Status</td></tr>
<tr><td>VCO_VC_DAC<td>0x0039</td><td>0x00</td><td>Current Setting from PLL Calibration Module</td></tr>
<tr><td>TXBYTES<td>0x003A</td><td>0x00</td><td>Underflow and Number of Bytes</td></tr>
<tr><td>RXBYTES<td>0x003B</td><td>0x00</td><td>Overflow and Number of Bytes</td></tr>
<tr><td>RCCTRL1_STATUS<td>0x003C</td><td>0x00</td><td>Last RC Oscillator Calibration Result</td></tr>
<tr><td>RCCTRL0_STATUS<td>0x003D</td><td>0x00</td><td>Last RC Oscillator Calibration Result</td></tr>
</table>
</body><html>

Note that you need to set up CC1150 with the same modulation format, deviation, and sync word length. The CC1100 is set up with 4 byte sync word; make sure CC1150 uses the same.

Other wireless

Other wireless technologies forum

SMARTRFTM-STUDIO: CC1100