CC2544: Can not write flash in 0x7c00(32 page)

Part Number: CC2544

Hi ,

I have met on issue : when I try to write flash Page31 and page 32like below code

1 run at IAR debug mode , All run OK; 

2 program by ""Flash programmer", the data in flash page 32 is OK, but the data in Flash page 32 is fail , please help to find out the issue

 __xdata uint8 ramdon_number[8];

/******************************************************************************
* @fn main
*
* @brief ...
*
* @return none
******************************************************************************/
void main(void) {

// Initialise board peripherals
halBoardInit();
Hal_getRnd(ramdon_number,8); //1st get 8 ramdon numbers

flash_dma_save((char *)ramdon_number,(unsigned short *)0x7800,8);
P0_1=~P0_1; //work done, save data into 0x7800 flash 

flash_dma_save((char *)ramdon_number,(unsigned short *)0x7C00,8);
P0_1=~P0_1; //this code not run, no data in flash 0x7C00 (Program by Flash Programer)

}

uint8 flash_dma_save(char *data_in,unsigned short *data_out,uint16 datasize)
{
DMA_DESC dmaConfig0;
/* Configure DMA channel 0:
* SRCADDR: address of the data to be written to flash (increasing).
* DESTADDR: the flash controller data register (fixed), so that the
* flash controller will write this data to flash.
* vlen: use LEN for transfer count.
* LEN: equal to the number of bytes to be transferred.
* WORDSIZE: each transfer should transfer one byte.
* TMODE: should be set to single mode (see datasheet, DMA Flash Write).
* Each flash write complete will re-trigger the DMA channel.
* TRIG: let the DMA channel be triggered by flash data write complete
* (trigger number 18). That is, the flash controller will trigger
* the DMA channel when the Flash Write Data register, FWDATA, is
* ready to receive new data.
* SRCINC: increment by one byte.
* DESTINC: fixed (always write to FWDATA).
* IRQMASK: disable interrupts from this channel.
* M8: 0, irrelevant since we use LEN for transfer count.
* PRIORITY: high.
*/
// bool ok_flag=false;
dmaConfig0.srcAddrH = ((uint16)data_in >> 8) & 0x00FF;
dmaConfig0.srcAddrL = (uint16)data_in & 0x00FF;
dmaConfig0.destAddrH = ((uint16)&FWDATA >> 8) & 0x00FF;
dmaConfig0.destAddrL = (uint16)&FWDATA & 0x00FF;
dmaConfig0.vlen = DMA_VLEN_USE_LEN;
dmaConfig0.lenH = (datasize >> 8) & 0x00FF;
dmaConfig0.lenL = datasize & 0x00FF;
dmaConfig0.wordSize = DMA_WORDSIZE_BYTE;
dmaConfig0.tMode = DMA_TMODE_SINGLE;
dmaConfig0.trig = DMA_TRIG_FLASH;
dmaConfig0.srcInc = DMA_SRCINC_1;
dmaConfig0.destInc = DMA_DESTINC_0;
dmaConfig0.irqMask = DMA_IRQMASK_ENABLE;
dmaConfig0.m8 = DMA_M8_USE_8_BITS;
dmaConfig0.priority = DMA_PRI_HIGH;

/* The DMA configuration data structure may reside at any location in
* unified memory space, and the address location is passed to the DMA
* through DMA0CFGH:DMA0CFGL.
*/
DMA0CFGH = ((uint16)&dmaConfig0 >> 8) & 0x00FF;
DMA0CFGL = (uint16)&dmaConfig0 & 0x00FF;

// Waiting for the flash controller to be ready.
while (FCTL & FCTL_BUSY);

/* Configuring the flash controller.
* FADDRH:FADDRL: point to the area in flash to write to.
*/
uint16 addr;
addr = (uint16)data_out >> 2; // You address 32-bit words through the flash controller.

FADDRH = (addr >> 8) & 0x00FF;
FADDRL = addr & 0x00FF;

// if(erase_flag)
// {
// // Erase the page that will be written to.
// FCTL |= FCTL_ERASE;
//
// // Wait for the erase operation to complete.
// while (FCTL & FCTL_BUSY);
// }

// Arm the DMA channel, takes 9 system clock cycles.
DMAARM |= DMAARM_DMAARM0;
NOP();NOP();NOP();NOP();NOP();NOP();NOP();NOP();NOP(); // 9 NOPs

// Enable flash write. Generates a DMA trigger.
FCTL |= FCTL_WRITE;

// Wait for DMA transfer to complete.
while (!(DMAIRQ & DMAIRQ_DMAIF0));

// Wait until flash controller not busy.
while (FCTL & (FCTL_BUSY | FCTL_FULL));

/* By now, the transfer is completed, so the transfer count is reached.
* The DMA channel 0 interrupt flag is then set, so we clear it here.
*/
DMAIRQ = ~DMAIRQ_DMAIF0; // Clear interrupt flag by R/W0, see datasheet.


// End function with infinite loop (for debugging purposes).
return true;
}