Last week doing some testing our code failed (stopped processing the sleep timer interrupt).
We have now produced a 150 lines assembler code example, with no includes, showing the problem.
The code setup a sleep timer for ca 2 sec, and flips a prot bit when it is handled.
Whatever it is working or not depends on some code alignment and port register writing. (please see comment in the code)
The code is tested on an CC2510EM 3.0 module from TI
; when running as expected it will toggle the p1.0 pin every second second
; and p1.3 will be held low at all time
; when it fails, p1 stops toggling
; stuff to change to see the problem:
; line 80-81: commenting out one or both of these lines changes if it runs or fails
; line 98: 0xa6 is ok to write to P0 but not 0xa8
; line 131: alignment of the "sleep" part of the sleep code seems to help
$NOMOD51 ; disable 8051 regs predefined by IDE
SFR P1DIR = 0xFE
SFR P1 = 0x90
SFR WORTIME0 = 0xA5
SFR WOREVT1 = 0xA4
SFR WOREVT0 = 0xA3
SFR CLKCON = 0xC6
SFR WORIRQ = 0xA1
SBIT STIE = 0xAD
SBIT EA = 0xAF
SFR P2 = 0xA0
SFR P0 = 0x80
SFR PSW = 0xD0
SBIT STIF = 0xC7
SFR DMA0CFGH = 0xD5
SFR DMA0CFGL = 0xD4
SFR DMAARM = 0xD6
SFR MEMCTR = 0xC7
SFR SLEEP = 0xBE
SFR DMAREQ = 0xD7
SFR PCON = 0x87
USING 0
ISEG AT 80h ; Declare a segment in Indirect addressable ram
STACK: DS 20h ; reserve 32 byte mem space (80h to 9Fh).
; Setup interrupt vectores
CSEG AT 0x00
LJMP START
CSEG AT 0x23
LJMP isr_not_implemented
; 5. ST (Sleep Timer Compare):
CSEG AT 0x2B
LJMP isr_st ; 3 bytes. 0x2E .. 0x30
CSEG AT 0x100
isr_not_implemented:
SETB p1.3
JMP isr_not_implemented
START: MOV SP,#STACK-1
; Set system clock to RC, 13MHz, leave all other settings:
MOV P1DIR,#0x09 ; P1.0 is flashing with 1 sec, p1.3 is indicating if other interrupts occure
; wait for wortimer edege
MOV A,WORTIME0
loop_2: CJNE A,WORTIME0,edge_2
JMP loop_2
edge_2: ; Setup 2 sec (approx) sleep timeout
MOV WOREVT1,#HIGH 33333d
MOV WOREVT0,#LOW 33333d
ORL WORIRQ,#00010000b ; Enable Sleep timer Module-int (EVENT0_MASK)
SETB STIE ; Enable Sleep Timer CPU-int. (IEN0.STIE)
SETB EA
;--------------------------------------------------------------------------------------------------------------------------------------
MOV P2,#00000011b ; commenting out this line, it will fail constantly
MOV P1,#01000011b ; commenting out this line, it always work also the upper line can be comment out
sleep_loop: CALL enter_sleep ; sleep test loop
jmp sleep_loop
RET
;*************************************** ISR_ST *************************************************************************
isr_st:
PUSH PSW
CLR STIF
ANL WORIRQ,#11111110b
CPL P1.0 ; toggeling p1.0 every secend sesend
MOV P0,#0xA6 ; is working moving 0xA6, failing if moving 0xA8 to p0 (p1 stops toggling)
POP PSW
RETI
enter_sleep:
; we are not testing if there is enough time because in this test ther is always enough time to sleep
MOV DMA0CFGH,#HIGH hiber_dma_conf ; (defined below)
MOV DMA0CFGL,#LOW hiber_dma_conf
MOV DMAARM,#0000$0001b ; Read configuration and arm channel 0
MOV A,WORTIME0
loop: CJNE A,WORTIME0,edge
JMP loop
edge: ORL MEMCTR,#00000010b ; Disable flash cache
MOV SLEEP, #00000110b ; Set PM2
NOP ; NOP is Required
NOP ; Required
NOP ; Required
; Timing critical code:
CALL sleep_now
RET
;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
_dma_data_pm2: DB 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x04
hiber_dma_conf: DW _dma_data_pm2
DB 0xDF, 0xBE, 0x00, 0x07, 0x20, 0x42
CSEG AT 0x6246 ; failing somtimes
;CSEG AT 0x624A ; working in all the examples
; alignment critical with 0x624A it seems to be working always
; Timing critical code:
sleep_now:
MOV DMAREQ,#0000$0001b ; Trigger channel 0 (PM2 only)
NOP ; allign DMA transfer precisely <<<<<<===================================================
ORL PCON,#0000$0001b ; Enter sleep
NOP ; After this NOP, the ISR is vectored
RET
END
