Other Parts Discussed in Thread: MSP430FR5994
Dear Sirs:
I'm having trouble receiving a standard packet and having the same trouble receiving encoded std packet.
IOCONFIG0 is set to 06. Its positive edge interrupts and runs the receiver. This occurs when sync has been received.
Its negative edge also interrupts and sets packetSemaphore to 01 . This should be when the packet has been all received. The rising and falling interrupts do occur and I’ve looked at gpio0 with a scope and it pulsed for 21ms (high, low) with packed length of about 10 characters, so the waveform seems to be
Working. However the receive routine below comes up with rxBytes of 0 every time. Have same problem with encrypted receive routine. I can put in delay and it will be able to read the bytes, but this should work as is.
Thanks for your help.
Receive routine for non encoded packet:
// Wait for packet received interrupt
while(!packetSemaphore)
A=A+1;
// Read number of bytes in RX FIFO
cc120xSpiReadReg(CC120X_NUM_RXBYTES, &rxBytes, 1);
// Check that we have bytes in FIFO
if(rxBytes != 0)
{
// Read MARCSTATE to check for RX FIFO error
cc120xSpiReadReg(CC120X_MARCSTATE, &marcState, 1);
//Mask out MARCSTATE bits and check if have RX FIFO ERR
if((marcState & 0x1F) == 0x11) //RX_FIFO_ERROR
{
// Flush RX FIFO
trxSpiCmdStrobe(CC120X_SFRX);
} else
{
// Read n bytes from RX FIFO
cc120xSpiReadRxFifo(rxBuffer, rxBytes);
// Check CRC ok (CRC_OK: bit7 in second status byte)
// This assumes status bytes are appended in RX_FIFO
// (PKT_CFG1.APPEND_STATUS = 1)
// If CRC is disabled the CRC_OK field will read 1
If(rxBuffer[rxBytes-1] & 0x80)
{
// Update packet counter
packetCounter++;
}
}
// Reset packet semaphore
packetSemaphore = ISR_IDLE;
// Set radio back in RX
trxSpiCmdStrobe(CC120X_SRX);
} //end of not encrypted receive
Config:
{CC120X_IOCFG0, 0x06}, //PKT_SYNC_RXTX
{CC120X_SYNC3, 0x55}, //DualSync
{CC120X_SYNC2, 0x59}, //These 2 syncs are used for receive only. Transmit sync is set prior to tx.
{CC120X_SYNC1, 0x56}, //
{CC120X_SYNC0, 0xa6}, //
{CC120X_SYNC_CFG0, 0x03}, //**was 88. added PQT_EN=80 & PQT_Gating_En=0x08,b00= most strict. b10=strict_sync_check=3
{CC120X_SYNC_CFG1, 0x28}, //**28=11 bits & 8 thresh. was 48. 4x=16bits, 8x=24bits, Ax=32 bits 7-5 len sync, 4:0=sync thresh
{CC120X_DEVIATION_M, 0x8D},
{CC120X_MODCFG_DEV_E, 0x08}, //08 for GFSK, 28 for 4GFSK GFSK/4FSK
{CC120X_DCFILT_CFG, 0x5D},
{CC120X_PREAMBLE_CFG1, 0x14}, //14=3bytes, 18=4b. 20=6b 10=2bytes e AA. was 24. 0x31=24bytes. 0x25=7bytes
{CC120X_PREAMBLE_CFG0, 0xb9}, //**was 8A PQT_EN=08
{CC120X_IQIC, 0xCB},
{CC120X_CHAN_BW, 0xA6}, //AC=9.46khz. AA=10khz
{CC120X_MDMCFG1, 0x40}, //was E0. 80=carrier sense gate, 40=fifo en, Man mode=20, invert data=10
{CC120X_MDMCFG0, 0x05},
{CC120X_SYMBOL_RATE2, 0x5F}, //4f for normal 2400= 5f, 4800=6f or 9600 w/o manchester
{CC120X_SYMBOL_RATE1, 0x75},
{CC120X_SYMBOL_RATE0, 0x10},
{CC120X_AGC_REF, 0x31},
{CC120X_AGC_CS_THR, 0x8B}, //8B=-117, 8C=-116, 8d=-115 8A=-118,88=-120 was 8a, 92=-110dbm. 8F=-113, A6=-90dbm
{CC120X_AGC_CFG1, 0x40},
{CC120X_AGC_GAIN_ADJUST, 0x9c}, //9C=-100, 9D=-99. This is the RSSI offset valid when AGC_GAIN_ADJUST.GAIN_ADJUSTMENT = 0x00.
{CC120X_AGC_CFG0, 0x8C}, //8c=5 counts. Was 80=1 count for rssi
{CC120X_FIFO_CFG, 0x00},
{CC120X_SETTLING_CFG, 0x03},
{CC120X_FS_CFG, 0x1B},
{CC120X_WOR_CFG0, 0x08}, //same
{CC120X_WOR_CFG1, 0x08}, //added
{CC120X_WOR_EVENT0_MSB, 0x01}, //0035=.6pre, 010A=1pre, 018f= 2pre, 0214=2.5pre, 029a=3pre
{CC120X_WOR_EVENT0_LSB, 0x8f}, //
{CC120X_PKT_CFG2, 0x00}, //0c=cca mode. CRc disabled, no status byte
//{CC120X_PKT_CFG1, 0x03}, //def=3, 0x01=append status. 20,10=Adx chk. 02(init ffff) and 04(init 0000) =crc enabled.
{CC120X_PKT_CFG0, 0x20}, //fixed length=00 in bits 6:5, bit len in bits 4:2
//{CC120X_RFEND_CFG1, 0x30}, // x30 gives return to rx after rxing
{CC120X_RFEND_CFG0, 0x04}, //04:RX termination based on PQT. 0x1: Rx term based on CS. 0x30 gives return to rx after txing
{CC120X_PKT_LEN, 0x7d}, //Maximum packet length
{CC120X_IF_MIX_CFG, 0x1C},
{CC120X_FREQOFF_CFG, 0x22}, //FOC_EN=x20, FOC_KI_Factor=02 was 20
{CC120X_MDMCFG2, 0x00},
{CC120X_TOC_CFG, 0x4b}, //** was 40 TOC limit 2%
{CC120X_SETTLING_CFG, 0x08}, //Cal FS going from idle to rec or tx
{CC120X_FREQ2, 0x5A},
{CC120X_FREQ1, 0x00},
{CC120X_FREQ0, 0x00},
{CC120X_IF_ADC1, 0xEE},
{CC120X_IF_ADC0, 0x10},
{CC120X_FS_DIG1, 0x07},
{CC120X_FS_DIG0, 0xAF},
{CC120X_FS_CAL1, 0x40},
{CC120X_FS_CAL0, 0x0E},
{CC120X_FS_DIVTWO, 0x03},
{CC120X_FS_DSM0, 0x33},
{CC120X_FS_DVC0, 0x17},
{CC120X_FS_PFD, 0x00},
{CC120X_FS_PRE, 0x6E},
{CC120X_FS_REG_DIV_CML, 0x1C},
{CC120X_FS_SPARE, 0xAC},
{CC120X_FS_VCO0, 0xB5},
//{CC120X_FS_CFG, 0x0B}, //136-160Mhz
{CC120X_XOSC5, 0x0E},
{CC120X_XOSC1, 0x03},
};