I have a CC1200 on a board, I can transmit and receive with it but I have some issues. I have the GPIO3 configured as Pkt_sync_rxtx, CC120X_IOCFG3, 0x06 but for some reason this pin always reads high and never gets triggered. Instead to detect packets I use the code
cc120xSpiReadReg(CC120X_PQT_SYNC_ERR, &PreSyncLevel, 1);
if (((PreSyncLevel&0xF))<10)
HadPre=1;
to detect if a sync has been detected and then delay to wait for the rest of the packet to arrive and then read the fifo. So if I am detecting the sync is there another register setting to get the GPIO3 to work as defined?
I used RF Studio to work out the register settings.
My other issue is it is not receiving at anywhere near the sensitivity level. I have to pump up the signal to about -31dBm to receive data. What register settings would affect this? Thanks for any help. These are my register settings:
// RX filter BW = 14.880952 kHz
// Address config = No address check.
// Packet length = Variable
// Symbol rate = 7.4 ksps
// Carrier frequency = 170MHz
// Bit rate = 7.4 kbps
// Packet bit length = 0
// Modulation format = 2-FSK
// Packet length mode = Variable
// Device address = 0
// Deviation = 3.681183 kHz
// PA Ramping = true
static const registerSetting_t preferredSettings[]=
{
{CC120X_IOCFG3, 0x06}, //pkt_sync_RXTX, GPIO3
{CC120X_IOCFG2, 0x01}, //RXfifo_thr_pkt - tells when a packet is received or above too many bytes, GPIO2
{CC120X_IOCFG1, 0x30}, //high Z for SO, GPIO1
{CC120X_IOCFG0, 0x02}, //txfifo_thr - tx fifo filled above a threshold, GPIO0
{CC120X_SYNC3, 0xD6},
{CC120X_SYNC2, 0xBA},
{CC120X_SYNC1, 0xD6},
{CC120X_SYNC0, 0x08}, //0xBA},
{CC120X_SYNC_CFG1, 0xAA}, //32 bit sync
{CC120X_SYNC_CFG0, 0x03}, //strict sync disabled, no preamble needed for sync
{CC120X_DEVIATION_M, 0xC1}, // fdev = 40e6*193/2^21
{CC120X_MODCFG_DEV_E, 0x00}, //normal modem mode, 2FSK
{CC120X_DCFILT_CFG, 0x5D},
{CC120X_PREAMBLE_CFG1, 0x28}, //8 byte preamble, 0xAA
{CC120X_PREAMBLE_CFG0, 0x8A}, //preamble detection enabled, 11 symbols till valid
{CC120X_IQIC, 0xCB},
{CC120X_CHAN_BW, 0x8E}, //0x87}, //60kHz //0x9C}, //ADC decimation factor = 48, BB Dec factor = 28
{CC120X_MDMCFG1, 0x40}, //always search for sync, fifo enabled, no manchestor (mdmCG2- 0=-dev, 1=+dev)
{CC120X_MDMCFG0, 0x05}, //transparent disabled, viterbi detection enabled
{CC120X_SYMBOL_RATE2, 0x68}, //7400 ksps
{CC120X_SYMBOL_RATE1, 0x3F},
{CC120X_SYMBOL_RATE0, 0x92},
{CC120X_AGC_REF, 0x2F}, //0x33}, //0x36}, //0x30},
{CC120X_AGC_CS_THR, 0xF7},
{CC120X_AGC_GAIN_ADJUST, 0x00},
{CC120X_AGC_CFG3, 0xA0}, //min and max gain set to 39dB
{CC120X_AGC_CFG2, 0x31},
{CC120X_AGC_CFG1, 0x52}, //0x40},
{CC120X_AGC_CFG0, 0x4F}, //0x83},
{CC120X_FIFO_CFG, 0x00},
{CC120X_DEV_ADDR, 0x00},
{CC120X_SETTLING_CFG, 0x03}, //auto cal is manual use SCAL strobe
{CC120X_FS_CFG, 0x1A}, //out of lock detector enabled, 136.7 to 160MHz band
//{CC120X_FS_CFG, 0x1B}, //out of lock detector enabled, 136.7 to 160MHz band
{CC120X_WOR_CFG1, 0x08}, //eWOR normal mode
{CC120X_WOR_CFG0, 0x20},
{CC120X_WOR_EVENT0_MSB, 0x03},
{CC120X_WOR_EVENT0_LSB, 0xA4},
{CC120X_RXDCM_TIME, 0x00},
{CC120X_PKT_CFG2, 0x00}, //fifo mode, normal mode
{CC120X_PKT_CFG1, 0x01}, //0x03}, //fec disabled, whitening enabled, no address check, crc, status appended
{CC120X_PKT_CFG0, 0x20}, //variable length pkt, no uart
{CC120X_RFEND_CFG1, 0x0F}, //goes to idle after good rx pkt, no rx timeout
{CC120X_RFEND_CFG0, 0x00}, //after tx goes to idle, rx bad pkt stays in rx, no antenna diversity or rx term
{CC120X_PA_CFG1, 0x3F}, //no power ramping //0x46},
{CC120X_PA_CFG0, 0x56},
{CC120X_ASK_CFG, 0x0F},
{CC120X_PKT_LEN, 0xFF}, //maximum pkt length 255, AFTER THIS IS EXTENDED ADDRESS SPACE
{CC120X_IF_MIX_CFG, 0x1C},
{CC120X_FREQOFF_CFG, 0x22}, //frequency offset correction enabled
{CC120X_TOC_CFG, 0x4B}, //0x0B},
{CC120X_MARC_SPARE, 0x00},
{CC120X_ECG_CFG, 0x00}, //divide clock by 64
{CC120X_MDMCFG2, 0x0C},
{CC120X_EXT_CTRL, 0x01},
{CC120X_RCCAL_FINE, 0x00},
{CC120X_RCCAL_COARSE, 0x00},
{CC120X_RCCAL_OFFSET, 0x00},
{CC120X_FREQOFF1, 0x00},
{CC120X_FREQOFF0, 0x00},
{CC120X_FREQ2, 0x55}, //170
{CC120X_FREQ1, 0x00},
{CC120X_FREQ0, 0x00},
//{CC120X_FREQ2, 0x52}, //137.485
//{CC120X_FREQ1, 0xB5},
//{CC120X_FREQ0, 0x25},
//{CC120X_IF_ADC2, 0x02},
//{CC120X_IF_ADC1, 0xEE},
//{CC120X_IF_ADC0, 0x10},
{CC120X_FS_DIG1, 0x07},
{CC120X_FS_DIG0, 0xAF},
{CC120X_FS_CAL3, 0x00},
{CC120X_FS_CAL2, 0x20},
{CC120X_FS_CAL1, 0x40},
{CC120X_FS_CAL0, 0x0E},
{CC120X_FS_CHP, 0x28},
{CC120X_FS_DIVTWO, 0x03},
{CC120X_FS_DSM1, 0x00},
{CC120X_FS_DSM0, 0x33},
{CC120X_FS_DVC1, 0xFF},
{CC120X_FS_DVC0, 0x17},
{CC120X_FS_LBI, 0x00},
{CC120X_FS_PFD, 0x00},
{CC120X_FS_PRE, 0x6E},
{CC120X_FS_REG_DIV_CML, 0x1C},
{CC120X_FS_SPARE, 0xAC},
{CC120X_FS_VCO4, 0x14},
{CC120X_FS_VCO3, 0x00},
{CC120X_FS_VCO2, 0x00},
{CC120X_FS_VCO1, 0x00},
{CC120X_FS_VCO0, 0xB5},
{CC120X_XOSC5, 0x0E},
{CC120X_XOSC4, 0xA0},
{CC120X_XOSC3, 0x03},
{CC120X_XOSC2, 0x04},
{CC120X_XOSC1, 0x03},
{CC120X_AGC_GAIN2, 0xD1},}; //use AGC
