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Original question:

CC1101-Q1: SO/GDO1 Pin high, device probably not entering PowerDown, high current measured, Not able to transmit

CC1101-Q1: CC1101-Q1

Norm HAMIDOVIC
Prodigy 40 points
Part Number: CC1101-Q1

64 IDLE 0 64 OK 65 IDLE 0 65 OK APPEND_STATUS = 1 CRC_EN = 1 66 RX 0 65 - FEC_EN = 0 67 RX 0 65 - 68 RXFIFO_OVERFIEW 1 65 OK

for the cc1101-q1  silicon errata and following setting

Does it mean that for variable packet lenght: pkt length of 66 or 67 bytes will result in the Rx state not transitioning to rx overflow?

so to test for this behavior and trigger this event and considering our radio settings, i.e  the append status==1 and CRC_EN ==1 FEC_EN==0.  should we be sending a packet with the packet length of A: 62 bytes as packet length, B: 63 bytes as packet lenght, C: 64, Bytes as packet lenght, D: 65 Bytes as packet lenght  or E: 66 bytes as packet length.

Also what would happen if 3 messages were received in the fifo i.e fifo wasn't read  in between the idle and going to RX again? would receiving 3 or 4 seperate messages without reading fifo in between result in same overflow error.

  • +1
    TI__Guru* 82421 points

    Assume you are using variable packet length mode and use the following:

    APPEND_STATUS = 1

    CRC_EN = 1

    FEC_EN = 0

    Sending a length byte of 61, means that 1 + 61 + 2 = 64 bytes are supposed to be put in the RX FIFO (length byte + payload bytes + 2 status bytes)

    That again means that length byte = 61 or 62 will be OK. length byte 63 and 64 will result in being stuck in RX, and length byte 65 and above will result in an overflow (given that the FIFO was empty when entering RX (it is the total number of 66 and 67 bytes received that is the problem)

    This will also give a problem if you receive two packets in a row without emptying the FIFO in-between:

    Length byte 3: 1 + 3 + 2 = 6 bytes to be received

    Length byte 58: 1 + 58 +2 = 61 bytes to be received

    This means that a total of 6 + 61 = 67 bytes are to be received, which will leave the radio stuck in RX (if the first packet is not read out of the FIFO before the next packet comes along).

    Siri

  • 0 in reply to Siri
    Prodigy 40 points

    Thank you Siri! Your in depth explanation and examples are greatly appreciated. We'll give this a go.