Other Parts Discussed in Thread: CC1310, LAUNCHXL-CC1310
Hi,
I'm trying to communicate a LAUNCHXL-CC1310 board with a custom board which uses a CC1101. I'm using the custom board on a proyect based on MPLAB, on the other hand I'm using smartrf studio to send packets as a Tx with the CC1310 board. I have the following radio configuration on MPLAB:
/**
* Main function for configuring the radio transceiver.
*
* IMPORTANT:
* The configuration collected in this function must
* be common to all modules in order to allow them to
* communicate with each other. If the configuration differs,
* communication failures are likely to occur.
*
* The default basic configuration is as follows:
*
* Modulation: GSK
* Communication channel: 0
* Carrier frequency: 868.0003MHz
* Data packet length: 62 Bytes
* Communication speed: 4800 kbps
* Channel bandwidth: 200kHz
* RX filter bandwidth: 350kHz
* Transmission power: +12dBm
* Physical address: Defined as a parameter
* Broadcasting: 0 and 255
* Error checking: CRC
*/
void CC1101setConfig(unsigned char address){
CC1101sendStrobe(CC1100_CMD_SIDLE);
/* Configure the power amplifier */
CC1101Write(CC1100_CFG_PA, 0xC0);
/* Set syncronization word */
CC1101Write(CC1100_CFG_SYNC1, 0x36);
CC1101Write(CC1100_CFG_SYNC0, 0x36);
/* Configure frequency calibration registers
* Fcarrier = Fosc · FREQ / 2^16
*
* F = 26E6 · 2187897 / 65535 = 868.014.373 Hz
*
*/
CC1101Write(CC1100_CFG_FREQ2, 0x21);
CC1101Write(CC1100_CFG_FREQ1, 0x62);
CC1101Write(CC1100_CFG_FREQ0, 0x77);
/* Configure frecuency sintetizator
*
* Fi = Fosc · Fosc / 2^10
*/
CC1101Write(CC1100_CFG_FSCTRL1, 0x06);
CC1101Write(CC1100_CFG_FSCTRL0, 0x00);
/* Registros de configuración del Modem */
/* Modem configuration 4
* 7:6 CHANBW_E
* 5:4 CHANBW_M
* 3:0 DRATE_E
*
* BW = fosc / (8 · (4 + CHANBW_M) · 2 ^ CHANBW_E)
*
* BW = 26E6 / (8 · (4 + 0) · 2^0 = 812,5 kHz
*
* 0000 0111 {07h}
* 0000 0101 {05h}
*
*/
CC1101Write(CC1100_CFG_MDMCFG4, 0x07);
/* Modem configuration 3
* Speed of the information transmission.
* 7:0 DRATE_M
*
* RD = Fosc · (256 + DRATE_M) · 2^DRATE_E / 2^28
*
* DRATE_E = 7
* DRATE_M = 131
*
* RD = 26E6 · (256 + 131) · 2^7 / 2^28 = 4797,93 (4800)
*
*/
CC1101Write(CC1100_CFG_MDMCFG3, 0x43);
/* Modem configuration 2
*
*
*/
CC1101Write(CC1100_CFG_MDMCFG2, 0x13);
CC1101Write(CC1100_CFG_MDMCFG1, 0xA3);
CC1101Write(CC1100_CFG_MDMCFG0, 0xF8);
/**
* Always use channel 0 for communication between modules
*
* @param address
*/
CC1101Write(CC1100_CFG_CHANNR, 0x00);
/**
* The deviation controls the maximum width of the spectrum that the signal occupies.
* that is being transmitted.
* @param address
*/
CC1101Write(CC1100_CFG_DEVIATN, 0x55);
CC1101Write(CC1100_CFG_FREND1, 0xB6);
CC1101Write(CC1100_CFG_FREND0, 0x10);
/**
* Frequency offset setting
*
* 7:6 Not used
* 5 FOC_BS_CS_GATE
* 4:3 FOC_PRE_K[1:0]
* 2 FOC_POST_K
* 1:0 FOC_LIMIT[1:0]
* @param address
*/
CC1101Write(CC1100_CFG_FOCCFG, 0x1B);
/**
* Bit Sync Settings
* BS_PRE_KI: 00 (1 x Ki)
* BS_PRE_KP: 01 (2 x Kp)
* BS_POST_KI: 1 (Ki/2)
* BS_POST_KP: 1 (Kp)
* BS_LIMIT: 00 (No data rate offset compensation performed)
* @param address
*/
CC1101Write(CC1100_CFG_BSCFG, 0x1C);
/**
* 43h - 0100 0011
* MAX_DVGA_GAIN (7:6): 01 (All gain setting can be used)
* MAX_LNA_GAIN (5:3): 000 (Maximum possible LNA + LNA 2 gain)
* MAGN_TARGET (2:0): 011 (33dB)
*
*/
CC1101Write(CC1100_CFG_AGCCTRL2, 0x43);
/**
* 40h - 0100 0000
* AGC_LNA_PRIORITY : 1 (LNA gain is decreased first)
* CARRIER_SENSE_REL_THR (5:4): 00 (Relative sense threshold disbaled)
* CARRIER_SENSE_ABS_THR (3:0): 0000 ()
*/
CC1101Write(CC1100_CFG_AGCCTRL1, 0x40);
/**
* B3h - 1011 0011
* HYST_LEVEL (7:6): 2 (Medium hysteresis)
* WAIT_TIME (5:4): 3 (32 samples)
* AGC_FREEZE (3:2): 0 (Normal operation)
* FILTER_LENGTH (1:0): 3 (64 channel filter samples)
*/
CC1101Write(CC1100_CFG_AGCCTRL0, 0xB3);
/**
* Frequency synthesizer calibration, record 3.
* Value: EAh (1110 1010)
* FSCAL3 (7:6) - 3h
* CHP_CURR_CAL_EN (5:4) - 2h
* FSCAL3 (3:0) - Ah
*
*/
CC1101Write(CC1100_CFG_FSCAL3, 0xEA);
/**
* Frequency synthesizer calibration, record 2.
* Value: EAh (1110 1010)
* VCO_CORE_H_EN - 1 {High VCO}
* FSCAL2 (4:0) - Ah {}
*/
CC1101Write(CC1100_CFG_FSCAL2, 0x2A);
/**
* Frequency synthesizer calibration, record 1.
* Value: EAh (1110 1010)
* @param address
*/
CC1101Write(CC1100_CFG_FSCAL1, 0x00);
/**
* Frequency synthesizer calibration, record 0.
* Value: EAh (1110 1010)
* @param address
*/
CC1101Write(CC1100_CFG_FSCAL0, 0x1F);
CC1101Write(CC1100_CFG_TEST0, 0x09);
/**
* Set the operating mode of the GDO2 output pin
* GDO2_INV: 0
* GDO2_CFG: 07h
*
* @param address
*/
CC1101Write(CC1100_CFG_IOCFG2, CC1100_GDx_CFG_RCV_CRCOK);
/**
* Set the operating mode of the GDO0 output pin
* GDO0_INV: 0h
* GDO0_CFG: 29h
*
* @param address
*/
CC1101Write(CC1100_CFG_IOCFG0, CC1100_GDx_CFG_CHIP_RDY); //0x80);
/* Packet control configuration */
/**
* CLOSE_IN_RX: 0h
* FIFO_THR: 0h
* @param address
*/
CC1101Write(CC1100_CFG_FIFOTHR, 0x00); /* 0 CAMBIADO TEST */
/**
* Size in bytes of the packet sent by radio
*
* @param address
*/
CC1101Write(CC1100_CFG_PKTLEN, 62); /* 62 CAMBIADO TEST */
/**
* Configura el primer registro de control de paquetes de radio
* PKTCTRL1.0:1 - Address check - Admite paquetes que viene en broadcast a 00h y FFh
* PKTCTRL1.2 - Append status -
* PKTCTRL1.3 - Enable FIFO flush with CRC check
*/
CC1101Write(CC1100_CFG_PKTCTRL1, 0x0B); /* 0x0D CAMBIADO TEST */
/**
* Configura el segundo registro de control de paquetes de radio
* WHITE_DATA (6): 1 (Aplica la función de Whitening)
* PKT_FORMAT (5:4): 0 (Paquete en modo normal usando el buffer para RX Y TX)
* CRC_EN (2): 1 (Activa la comprobación por CRC)
* LENGTH_CONFIG (1:0): 0 (Configura la longitud del paquete como fija)
* @param address
*/
CC1101Write(CC1100_CFG_PKTCTRL0, 0x44); /* 0x44 CAMBIADO TEST */
/**
* Configura la dirección para la comunicación
* @param address
*/
CC1101Write(CC1100_CFG_ADDR, address);
/* CONFIGURACIÓN DE LA MAQUINA DE ESTADOS PRINCIPAL DE RADIO */
/**
* Configura el tercer byte de la máquina de estados
* RX_TIME_RSSI (4): 0
* RX_TIME_QUAL (3): 0
* RX_TIME (2:0): 7
* Comentada porque se usa la configuración por defecto
*/
//CC1101Write(CC1100_CFG_MCSM2, 0x07);
/**
* Configura el segundo byte de la máquina de estados
* 3Fh - 0011 1111
* CCA_MODE (5:4): 3 {If RSSI below threshold currently receiving a packet}
* RXOFF_MODE (3:2): 3 {Stay in RX}
* TXOFF_MODE (1:0): 3 {Next state after finishing packet transmission RX}
* @param address
*/
CC1101Write(CC1100_CFG_MCSM1, 0x0F); //0x3F Cambiado el 24/06/2021
/**
* Configura el primer byte de la máquina de estados
* 18h - 0001 1000
* FS_AUTOCAL (5:4): 1 {When going from IDLE to TX or TX (or FSTXON)}
* PO_TIMEOUT (3:2): 2 {Timeout after XOSC start approx. 149~155uS}
* PIN_CTRL_EN : 0 {Disables the pin radio control option}
* XOSC_FORCE_ON : 0 {Not forces the XOSC to stay on in the SLEEP state}
* @param address
*/
CC1101Write(CC1100_CFG_MCSM0, 0x18);
/* Limpia los buffers TX y RX */
CC1101sendStrobe(CC1100_CMD_SFTX);
CC1101sendStrobe(CC1100_CMD_SFRX);
/* Coloca el transceiver en el modo receptor */
CC1101setMode(CC1100_MODE_RX);
}
And the settings in smartrf:
