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CC1352P7: GPIO configuration when powered off

ddb
Intellectual 464 points
Part Number: CC1352P7


Hello,

I have a product using the CC1352 MCU. During production I need to test the PCB components by applying voltages on some nets, these nets sometimes are connected directly to the MCU GPIOs while the board is powered off. 

The questions are:

- What is the state of the MCU GPIOS when it's not powered? Are they in high impedance state? 

- Is it safe to apply a voltage on powered off MCU? If not, then what's the recommended approach?

Thanks.

  • 0
    TI__Mastermind 18475 points

    Hi,

    From Chapter 13.5 of SWCU192 (CC13x7, CC26x7 SimpleLink Wireless MCU Technical Reference Manual): https://www.ti.com/lit/swcu192 : 

    By default, the I/O driver (output) and input buffer (input) are disabled (tri-state mode) at power on or reset, and thus the I/O pin can safely be left unconnected (floating).

    If the I/O pin is in a tri-state condition and connected to a node with a different voltage potential, a small leakage current can go through the pin. The same applies to an I/O pin configured as input, where the pin is connected to a voltage source (for example VDD/2). The input is then an undefined value of either 0 or 1.

    and Section 13.9.1 states:

    Both the input and the output buffer can be enabled or disabled at the same time. By disabling the output buffer the corresponding I/O pin will be in the tri-state condition (high impedance). If nothing is driving the I/O to a valid logical level when the output buffer is disabled then disable the input buffer to avoid excessive current draw through the I/O input buffer. Section 13.9.1.2 describes the I/O pin configuration in more detail.

    You can refer to Section 7.1 of the CC1352P7 Datasheet: https://www.ti.com/lit/swrs251 for the absolute maximum ratings for the device pins.

    Regards,

    Zack

  • 0 in reply to ZC
    Intellectual 464 points

    Hi Zack,

    Thanks for the answer, I've already been through those sections before. But I didn't think they were absolutely clear for my application in particular.

    For example "the I/O pin can safely be left unconnected" is not the same as safely applying a voltage on a random GPIO.

    Then while testing an assembled PCB with an already programmed MCU on it, I will not be able to change registers to enable or disable Input and output buffers. So while powered off, can I be sure the GPIOs are in tri-state? Or is there a way to temporarily and quickly disable the buffers during the assembly line testing?

    Thanks

  • 0 in reply to ddb
    TI__Mastermind 18475 points

    These are the absolute maximum ratings for the DIO pins (from the CC1352P7 datasheet):

    So, any applied voltage needs to be within this specification (including when VDDS = 0V).

    Section 11.5 of the TRM discusses your second question:

    The I/O configurations and states can be retained when the MCU and/or AUX domain is powered off. Before powering down the MCU domain, the pin configuration and output values from MCU peripherals mapped to pins (DIOs) through the MCU IOC must be latched in AON IOC. This is done by disabling the transparent mode in the AON_IOC:IOLATCH register. Before enabling the transparent mode after MCU is powered up again, the MCU IOC configuration must be reconfigured to the state it was in before power down

    The default state, however, is tri-state mode (with the input buffer disabled).

    There is also the gpioshutdown example which may be of use here: https://dev.ti.com/tirex/explore/node?node=A__ACBSX-sC9pUe5xA-x9Ssdg__com.ti.SIMPLELINK_CC13XX_CC26XX_SDK__BSEc4rl__LATEST&placeholder=true 

    Regards,

    Zack