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CC2510: Internal 8051 command cycles are not accurate as the datasheet states

spachner
Expert 1535 points
Other Parts Discussed in Thread: CC2510

Hi,

I am trying to write cycle accurate routine and tried the following:

CLR  0x84    ;3 cycles

SETB  0x84   ;3 cycles; 1st rising edge

CLR  0x84    ;3 cycles

SETB  0x84   ;3 cycles; 2nd rising edge

CLR  0x84    ;3 cycles

My CC2510 is driven by a 26MHz crystal, so the internal 8051 core runs with 26/2=13MHz and each machine cycle takes therefore 77 ns. Both command CLR and SETB needs according to the datasheet 3 cycles. So I expected that the interval between the first and seconds rising edge is (3+3)*77ns=462ns, but I see at the oscilloscope about 300ns.

Why? Is the datasheet wrong or my assumptions?

regards

spachner

  • 0
    TI__Guru* 86731 points

    Hi

    Try to set MEMCTR.PREFDIS = 0

  • 0 in reply to Siri
    Expert 1535 points

    Yes, changing the settings in MEMCTR is influencing the timing of my sample program. I forgot that the 8051 has a (prefetchable) cache which is probably the reason for being faster than my theoretically calculations. I assume that the 8051 has some pipeline inside which will influence the timing, too.

    Is there any reason why the MEMCTR.PREFDIS bit is not cleared upon reset like the CACHDIS is? I am going to clear the PREFDIS im my application to speed up. Any concerns from your side?

    regards

    spachner

  • 0 in reply to spachner
    TI__Mastermind 21125 points

    Spachner,

    Not sure what the design choise for doing prefetch disabled as the reset state is, can be "better safe than sorry" was the reason in case prefetching did not work as planned, but since it does there is now concern in changing. Just be aware that pre-fetching introduces a consumption penalty (which can be countradicted by staing less time in active due to the increased speed).

     

    Regards,
    Kjetil