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EM430F6137RF900 falsely indicating that sync word and packet received

Other Parts Discussed in Thread: TEST2, CC1125

Hello,

I'm currently working on a project using the EM430F6137RF900 kit. I have pretty much the same problem as in this thread http://e2e.ti.com/support/low_power_rf/f/156/t/272748.aspx , however the solution stated there doesn't seem to work in my case. 

I'm simply trying to run the Variable_GT_FIFO example for this kit. The only modification I've done is to the RF settings to be compliant with Wireless Mbus standard (mode T) and I've changed the ACLK source to REFOCLK since I haven't soldered the external crystal (there won't be enough room for it on the PCB in the final application so I'm trying to avoid using it now).

Why could the interrupt still be generated?


My RF setting are:

0x08, // FSCTRL1 Frequency synthesizer control.
0x00, // FSCTRL0 Frequency synthesizer control.
0x21, // FREQ2 Frequency control word, high byte.
0x6B, // FREQ1 Frequency control word, middle byte.
0xD0, // FREQ0 Frequency control word, low byte.
0x5C, // MDMCFG4 Modem configuration. - 103 kBaud
0x04, // MDMCFG3 Modem configuration.
0x05, // MDMCFG2 Modem configuration.
0x22, // MDMCFG1 Modem configuration.
0xF8, // MDMCFG0 Modem configuration.
0x00, // CHANNR Channel number.
0x44, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
0xB6, // FREND1 Front end RX configuration.
0x10, // FREND0 Front end RX configuration.
0x18, // MCSM0 Main Radio Control State Machine configuration.
0x2E, // FOCCFG Frequency Offset Compensation Configuration.
0xBF, // BSCFG Bit synchronization Configuration.
0x43, // AGCCTRL2 AGC control.
0x09, // AGCCTRL1 AGC control.
0xB5, // AGCCTRL0 AGC control.
0xEA, // FSCAL3 Frequency synthesizer calibration.
0x2A, // FSCAL2 Frequency synthesizer calibration.
0x00, // FSCAL1 Frequency synthesizer calibration.
0x1F, // FSCAL0 Frequency synthesizer calibration.
0x59, // FSTEST Frequency synthesizer calibration.
0x81, // TEST2 Various test settings.
0x35, // TEST1 Various test settings.
0x09, // TEST0 Various test settings.
0x47, // FIFOTHR RXFIFO and TXFIFO thresholds.
0x29, // IOCFG2 GDO2 output pin configuration.
0x06, // IOCFG0D GDO0 output pin configuration. Refer to SmartRF® Studio User Manual for detailed pseudo register explanation.
0x04, // PKTCTRL1 Packet automation control.
0x04, // PKTCTRL0 Packet automation control.
0x00, // ADDR Device address.
0xFF // PKTLEN Packet length. maximum bytes


  • By looking at 

    0x05, // MDMCFG2 Modem configuration.

    I conclude that you are using 15 bits out of 16 bits for sync word, then means that you allow 1 bit error and still you will accept the packet. This will wake up the radio pretty often because 1/32768 solutions of pure noise will match incoming sync word.

    I recommend using 32/32 as a default setting.

    Regards,
    /TA 

  • Note that the preamble + sync for T mode is nx(01)0000111101 where n>19 so you have to set up the chip for 2 byte sync. This is a short sync word and since CC430 allow 1 bit error out of 16 you will get a fair amount of false syncs. To avoid this you have to use CC1125.

  • Dear  TA12012  and TER,

    thank you both for your replies. That even explains the fact that the interrupt was being generated at pretty much random times.