I am using two cc1101 for Tx and Rx in 410 Mhz. I set Rx in asynchronous mode and Tx in FIFO mode. When I send data in 100 Kbit/s by FIFO I can receive data on GDO0 pin in receiver but when I send data in 500 Kbit/s by FIFO I can't receive data.
I check by spectrum analyzer and see signal spectrum. In 100Kbit/s I can see FSK signal but in 500kbit/s I see carrier with lines similar pulse signal spectrum.
100 kBits/s
500 kBit/s
This is my code (SPI CLK is 8 Mhz):
#define FSCTRL1_val 0x06 // Frequency synthesizer control.
#define FSCTRL0_val 0x00 // Frequency synthesizer control.
#define FREQ2_val 0x0F // Frequency control word, high #define. Fc=410 mhz
#define FREQ1_val 0xC4 // Frequency control word, middle #define.
#define FREQ0_val 0xEC // Frequency control word, low #define.
#define MDMCFG4_val 0x0E // Modem configuration.
#define MDMCFG3_val 0x3B // Modem configuration.
#define MDMCFG2_val 0x10 // Modem configuration.
#define MDMCFG1_val 0x01 // Modem configuration.
#define MDMCFG0_val 0xF8 // Modem configuration.
#define DEVIATN_val 0x75 // Modem deviation setting (when FSK modulation is enabled). Deviation=50 khz
#define FREND1_val 0x56 // Front end RX configuration.
#define FREND0_val 0x10 // Front end RX configuration.
#define MCSM2_val 0x0A // Main Radio Control State Machine configuration
#define MCSM1_val 0x3C // Main Radio Control State Machine configuration
#define MCSM0_val 0x08 // Main Radio Control State Machine configuration
#define FOCCFG_val 0x16 // Frequency Offset Compensation Configuration.
#define BSCFG_val 0x6C // Bit synchronization Configuration.
#define AGCCTRL2_val 0x03 // AGC control.
#define AGCCTRL1_val 0x40 // AGC control.
#define AGCCTRL0_val 0x91 // AGC control.
#define FSCAL3_val 0xE9 // Frequency synthesizer calibration.
#define FSCAL2_val 0x2A // Frequency synthesizer calibration.
#define FSCAL1_val 0x00 // Frequency synthesizer calibration.
#define FSCAL0_val 0x1F // Frequency synthesizer calibration.
#define PKTCTRL1_val 0x88 // Packet automation control.
#define PKTCTRL0_val 0x00 // Packet automation control.
#define PKTLEN_val 0x3C // Packet length.
#define IOCFG2_val 0x0D // GDO2 output pin configuration
#define IOCFG1_val 0x2E // GDO1 output pin configuration
#define IOCFG0_val 0x06 // GDO0 output pin configuration
#define FSTEST_val 0x59 // Frequency synthesizer calibration control
#define CHANNR_val 0x00 // Channel number.
#define TEST2_val 0x88 // Various test settings.
#define TEST1_val 0x31 // Various test settings.
#define TEST0_val 0x0B // Various test settings.
#define ADDR_val 0x00 // Device address.
#define FIFOTHR_val 07 // RX FIFO and TX FIFO thresholds
#define SYNC1_val 0xD3 // Sync word, high byte
#define SYNC0_val 0x91 // Sync word, low byte
#define WOREVT1_val 0x87 // High #define Event 0 timeout
#define WOREVT0_val 0x6B // Low #define Event 0 timeout
#define WORCTRL_val 0xFB // Wake On Radio control
#define RCCTRL1_val 0x41 // RC oscillator configuration
#define RCCTRL0_val 0x00 // RC oscillator configuration
#define PTEST_val 0x7F // Production test
#define AGCTEST_val 0x3F // AGC test
void send_packet (unsigned char length,unsigned char send_data[]){
write_burst_reg(FIFO,length,send_data);
write_strobe(STX); // send data into the transmit mode
while (!VPORT3_IN.0) // Wait for GDO0 to be set -> sync transmitted
write_strobe(SNOP);
while (VPORT3_IN.0);
write_strobe(SIDLE);
write_strobe(SFTX);
}
for(q=0;q<62;q++)
pulse[q]=0x55;
delay_us(100);
SET_SPIC_SS_LOW;
while(VPORT2_IN.6);
write_strobe(SRES);
while(VPORT2_IN.6);
RF_setting();
delay_us(100);
write_strobe(SCAL);
delay_us(900);
while (1)
{
send_packet (60,pulse);
}
}
What is the problem in 500Kbit/s ?
Thanks for helps
Best Regards
