CC1350: CCFG_FORCE_VDDR_HH parameter changed on collector example from SDK

Jorick Astrego

Intellectual 760 points

Part Number: CC1350

Dear all,

While merging the new coprocessor example from SDK 1.60 to SDK 2.20 for the CC1350 launchpad, I noticed

CCFG_FORCE_VDDR_HH=0

changed to

CCFG_FORCE_VDDR_HH=1

In the predefined symbols.

From what I read is that the board is then set to 1.95 external LDO mode. How can this work as the pcb of the launchpad hasn't changed.

We use the firmware on a custom pcb that provides 3.3v so should we leave it at 0?

over 7 years ago

0 TER over 7 years ago

TI__Guru**** 317180 points

If you use CCFG_FORCE_VDDR_HH=0 the max output power is 12.5 dBm, for CCFG_FORCE_VDDR_HH=1 the max output power is 14 dBm (see notes in the code export from SmartRF Studio etc)

1.65 V/ 1.95 V is the output voltage of the builtin LDO/ DCDC and this voltage is set by CCFG_FORCE_VDDR_HH and is a software setting.

0 Jorick Astrego over 7 years ago in reply to TER

Intellectual 760 points

Yes that I know.

So why does it change on the coprocessor example for the CC1350 launchpad between SDK versions?

0 TER over 7 years ago in reply to Jorick Astrego

TI__Guru**** 317180 points

I haven't been able to find out exactly why the change has been made. I have gotten information that implies that the change has been done to get the wanted output power on the antenna. It could be to compensate for the loss in the switch and the antenna used on the LP.

0 Jorick Astrego over 7 years ago in reply to TER

Intellectual 760 points

Well that is weird. In the technical reference manual I read that the cc13x0 devices have to be set to external regulator mode with a voltage range from 1.65v to 1.95v.

From what I know the launchpad is powered with the internal dc/dc converter on 3.3v....

0 TER over 7 years ago in reply to Jorick Astrego

TI__Guru**** 317180 points

- External regulator mode: Described in 1.3.13.3 (www.ti.com/.../swcu117h.pdf ) This is a mode typically used if the system has a 1.8 V regulator
- For the other modes, VDDS is between 1.8 V and 3.8 V. VDDR will then be either 1.65 V ( CCFG_FORCE_VDDR_HH=0) or 1.95 V ( CCFG_FORCE_VDDR_HH=1) in this mode. A LDO and a DCDC is placed in parallel in the chip and VDDR is given by either the LDO or DCDC dependent on the settings in CCFG.c.

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CC1350: CCFG_FORCE_VDDR_HH parameter changed on collector example from SDK