CC1200: Not receiving longer messages

Dear Sirs:

My cc1200 seem to be working very well on shorter message lengths like 2.5 bytes. 

I am using 11 bit sync and preamble_CFG1 is set to 3 bytes, Manchester encoded, fixed length message, no crc, sniff mode.  Right after the sync is a message identifier that indicates which type of message it is.

     So during receive the sync interrupts the processor which then runs the receive routine.  The receiver polls on the Num_rxbytes.  When the first byte arrives the receiver reads one byte (the message identifier) then sets pktlen to the required length to receive the rest of the packets.   The software then polls on the Num_RXBYTES until the rest of the bytes arrive in the FIFO, then they are read into the rxBuffer[].  The rest of the packets are now in rxBuffer[0], rxBuffer]1] , etc.  This all seems to work.  The message identifier byte, and first 3 bytes on the second read are always correct. 

     But with a longer message the cc1200 receiver does receive correctly a message sent from another cc1200.

     However when the same message is sent from a different older transmitter the cc1200 starts missing the 5^th, 6^th, 7^th, and 8^th packets on the second read.  I monitor the transmissions with a different receiver (not cc1200) and can tell that the older transmitter IS sending all the packets correctly (even though there are slight timing differences). 

     It is a mystery to me what could be going wrong.

Thanks for any help.

John

 The config is:

const registerSetting_t preferredSettings[]=

{

  //{CC120X_IOCFG3,            0x3c},         //dec 60.  read ext osc enable.  Doesn't work

  {CC120X_IOCFG2,            0x06},         //sniff 150M

  //{CC120X_IOCFG1,            0x00},         //make GPIO1 output & invert to high (see 3.4)

  {CC120X_IOCFG0,            0x06},

  {CC120X_SYNC3,             0x55},         //was AA, 55 7:0 sets MSB sync.  AA for inverted

  {CC120X_SYNC2,             0x55},         //was AA, 55, 7:0 sets MSB sync.

  {CC120X_SYNC1,             0x55},         //was AA, 55, 05 7:0 sets MSB sync.

  {CC120X_SYNC0,             0x56},         //was A9, 56 sets lsb of sync in 7:0.  Orig A6

  {CC120X_SYNC_CFG0,         0x88},         //was 88.  added PQT_EN & PQT_Gating_En, strict_sync_check=3

  {CC120X_SYNC_CFG1,         0x28},         //28=11 bits & 8 thresh.  was 48.  4x=16bits, 8x=24bits, Ax=32 bits 7-5 len sync, 4:0=sync thresh

  {CC120X_DEVIATION_M,       0x8D},

  {CC120X_MODCFG_DEV_E,      0x08},

  {CC120X_DCFILT_CFG,        0x5D},

  {CC120X_PREAMBLE_CFG1,     0x18},         //18=3b e aa.  10=2bytes e AA.  was 24.  0x31=24bytes. 0x25=7bytes

  {CC120X_PREAMBLE_CFG0,     0x8A},

  {CC120X_IQIC,              0xCB},

  {CC120X_CHAN_BW,           0x95},

  {CC120X_MDMCFG1,           0x60},     //40=fifo en, Man mode=20, invert data=10

  {CC120X_MDMCFG0,           0x05},

  {CC120X_SYMBOL_RATE2,      0x4F},

  {CC120X_SYMBOL_RATE1,      0x75},

  {CC120X_SYMBOL_RATE0,      0x10},

  {CC120X_AGC_REF,           0x31},

  {CC120X_AGC_CS_THR,        0x09},

  {CC120X_AGC_CFG1,          0x40},

  {CC120X_AGC_CFG0,          0x83},

  {CC120X_FIFO_CFG,          0x00},

  {CC120X_SETTLING_CFG,      0x03},

  {CC120X_FS_CFG,            0x1B},

  {CC120X_WOR_CFG0,          0x08},     //same

  {CC120X_WOR_CFG1,          0x08},     //added

  {CC120X_WOR_EVENT0_MSB,    0x02},     //3B pre. was 01.  was 02

  {CC120X_WOR_EVENT0_LSB,    0x9a},     //3b pre. was 8f for 2bytws.  was e2

  {CC120X_PKT_CFG2,          0x00},      //norm mode, CRc disabled, no status byte

  {CC120X_PKT_CFG1,          0x0},       // adx check & crc disabled.  This line needed to rec MCDT!

  {CC120X_PKT_CFG0,          0x10},      //x18 pro 6bits, x10 EMIDS 4bits.  fixed length=00 in bits 6:5, bit len in bits 4:2

  //{CC120X_RFEND_CFG1,        0x30},    // x30 gives return to rx after rxing

  {CC120X_RFEND_CFG0,        0x0C},      //0x30 gives return to rx after txing

  {CC120X_PKT_LEN,           0x08},      //pktlen, packet length 02 +4 bits for emids, 6-3/4 for pro

  {CC120X_IF_MIX_CFG,        0x1C},

  {CC120X_FREQOFF_CFG,       0x22},      //FOC_EN=x20, FOC_KI_Factor=02 was 20

  {CC120X_MDMCFG2,           0x0C},

  //{CC120X_TOC_CFG,           0x44},     //TOC limit 2% no diff to msg gen

  {CC120X_FREQ2,             0x5A},

  {CC120X_FREQ1,             0x00},

  {CC120X_FREQ0,             0x00},

  {CC120X_IF_ADC1,           0xEE},

  {CC120X_IF_ADC0,           0x10},

  {CC120X_FS_DIG1,           0x07},

  {CC120X_FS_DIG0,           0xAF},

  {CC120X_FS_CAL1,           0x40},

  {CC120X_FS_CAL0,           0x0E},

  {CC120X_FS_DIVTWO,         0x03},

  {CC120X_FS_DSM0,           0x33},

  {CC120X_FS_DVC0,           0x17},

  {CC120X_FS_PFD,            0x00},

  {CC120X_FS_PRE,            0x6E},

  {CC120X_FS_REG_DIV_CML,    0x1C},

  {CC120X_FS_SPARE,          0xAC},

  {CC120X_FS_VCO0,           0xB5},

  //{CC120X_FS_CFG,            0x0B},                     //136-160Mhz

  {CC120X_XOSC5,             0x0E},

  {CC120X_XOSC1,             0x03},

};