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CC1200EMK-420-470: RSSI value

Part Number: CC1200EMK-420-470
Other Parts Discussed in Thread: CC1200,


Using smartRF I'm sending packets directly through cable to cc1200 and trying to read RSSI value from RSSI[11:0] register. Here are the values (in dbm):

smartRF dBm ------> RSSI in cc1200 receiver

-40 ---> 22

-24 ---> 33.5

-12 ---> 33.5

-11 ---> 33.5



14 ---> 33.5

looks like an overflow?

I tried to send less than -40dbm by disconnecting the cable and I read some negative value.


Is there something I missed it?

  • Please see figure 4.3 in

    The RSSI you read from the register has to be adjusted. See SmartRF Studio to get the RSSI offset. See

  • Thank you TER for your response.

    I know that there is an offset and the value need to be adjusted. My concern is that it seems there is a threshold or somehow overflow in the RSSI value, somewhere between (-40 and -30 dBm).  

    I can NOT read more than that for example( -10, -5, 0 , 2 dbm).

    So, the highest value RSSI can read is somewhere between (-40 and -30 dBm).

    Do I need to set a threshold value for RSSI or something like that?

    Note: I'm using two "CC1200EMK-420-470" boards. One connected to the evaluation board and smartRF as TX. The other board connected to my MCU and used as RX where I'm reading the RSSI.

  • The RSSI saturates for input signals above ~- 7 dBm as the figure I pointed to show. Which settings do you use for this test? 

  • here are my settings:

    halRfWriteReg(&SpiHandle, IOCFG2,0x14, 0);              //GPIO2 IO Pin Configuration
    halRfWriteReg(&SpiHandle, SYNC_WORD3,0x93, 0);
    halRfWriteReg(&SpiHandle, SYNC_WORD2,0x0B, 0);
    halRfWriteReg(&SpiHandle, SYNC_WORD1,0x51, 0);
    halRfWriteReg(&SpiHandle, SYNC_WORD0,0xDE, 0);
    halRfWriteReg(&SpiHandle, SYNC_CFG1,0xAB, 0);   //Sync Word Detection Configuration Reg. 1
    halRfWriteReg(&SpiHandle, SYNC_CFG0,0x03, 0);    //Sync Word Detection Configuration Reg. 0
    halRfWriteReg(&SpiHandle, DEVIATION_M,0x79, 0); //Frequency Deviation Configuration
    halRfWriteReg(&SpiHandle, MODCFG_DEV_E,0x82, 0); //Modulation Format and Frequency Deviation Configur..
    halRfWriteReg(&SpiHandle, DCFILT_CFG,0x4B, 0);   //Digital DC Removal Configuration
    halRfWriteReg(&SpiHandle, PREAMBLE_CFG1,0x14, 0);
    halRfWriteReg(&SpiHandle, PREAMBLE_CFG0,0x8F, 0); //Preamble Detection Configuration Reg. 0
    halRfWriteReg(&SpiHandle, IQIC,0xD8, 0);                       //Digital Image Channel Compensation Configuration
    halRfWriteReg(&SpiHandle, CHAN_BW,0x13, 0);             //Channel Filter Configuration
    halRfWriteReg(&SpiHandle, MDMCFG1,0x40, 0);
    halRfWriteReg(&SpiHandle, MDMCFG0,0x05, 0);            //General Modem Parameter Configuration Reg. 0
    halRfWriteReg(&SpiHandle, SYMBOL_RATE2,0x8f, 0);  //Symbol Rate Configuration Exponent and Mantissa [1..
    halRfWriteReg(&SpiHandle, SYMBOL_RATE1,0x75, 0); //Symbol Rate Configuration Mantissa [15:8]
    halRfWriteReg(&SpiHandle, SYMBOL_RATE0,0x08, 0); //Symbol Rate Configuration Mantissa [7:0]
    halRfWriteReg(&SpiHandle, AGC_REF,0x41, 0);            //AGC Reference Level Configuration
    halRfWriteReg(&SpiHandle, AGC_CS_THR,0xF6, 0);    //Carrier Sense Threshold Configuration
    halRfWriteReg(&SpiHandle, AGC_CFG3,0x00, 0);
    halRfWriteReg(&SpiHandle, AGC_CFG2,0x00, 0);
    halRfWriteReg(&SpiHandle, AGC_CFG1,0x12, 0);        //Automatic Gain Control Configuration Reg. 1
    halRfWriteReg(&SpiHandle, AGC_CFG0,0x80, 0);       //Automatic Gain Control Configuration Reg. 0
    halRfWriteReg(&SpiHandle, FIFO_CFG,0xE0, 0);        //FIFO Configuration
    //halRfWriteReg(&SpiHandle, SETTLING_CFG,0x0B, 0);
    halRfWriteReg(&SpiHandle, FS_CFG,0x14, 0);           //Frequency Synthesizer Configuration
    //halRfWriteReg(&SpiHandle, WOR_CFG1,0x08, 0);
    //halRfWriteReg(&SpiHandle, WOR_CFG0,0x21, 0);
    halRfWriteReg(&SpiHandle, PKT_CFG2,0x00, 0); //Packet Configuration Reg. 2
    halRfWriteReg(&SpiHandle, PKT_CFG1,0x43, 0); //Packet Configuration Reg. 1
    halRfWriteReg(&SpiHandle, PKT_CFG0,0x20, 0); //Packet Configuration Reg. 0
    halRfWriteReg(&SpiHandle, RFEND_CFG1,0x0F, 0); //RFEND Configuration Reg. 0
    halRfWriteReg(&SpiHandle, RFEND_CFG0,0x00, 0);

    halRfWriteReg(&SpiHandle, PA_CFG1,0x01, 0); //Power Amplifier Configuration Reg. 1
    halRfWriteReg(&SpiHandle, PA_CFG0,0x20, 0);
    halRfWriteReg(&SpiHandle, PKT_LEN,0xFF, 0); //Packet Length Configuration
    halRfWriteReg(&SpiHandle, IF_MIX_CFG,0x1C, 1); //IF Mix Configuration
    halRfWriteReg(&SpiHandle, FREQOFF_CFG,0x00, 1); //Frequency Offset Correction Configuration
    halRfWriteReg(&SpiHandle, TOC_CFG,0x0B, 1); //Timing Offset Correction Configuration
    halRfWriteReg(&SpiHandle, MDMCFG2,0x02, 1); //General Modem Parameter Configuration Reg. 2
    halRfWriteReg(&SpiHandle, FREQ2,0x56, 1); //Frequency Configuration [23:16]

    halRfWriteReg(&SpiHandle, FREQ1,0x89, 1); //Frequency Configuration [15:8]
    halRfWriteReg(&SpiHandle, FREQ0,0x5E, 1);
    halRfWriteReg(&SpiHandle, IF_ADC2,0x00, 1);
    halRfWriteReg(&SpiHandle, IF_ADC1,0x00, 1); //Analog to Digital Converter Configuration Reg. 1
    halRfWriteReg(&SpiHandle, IF_ADC0,0x00, 1); //Analog to Digital Converter Configuration Reg. 0
    halRfWriteReg(&SpiHandle, FS_DIG1,0x07, 1); //Frequency Synthesizer Digital Reg. 1
    halRfWriteReg(&SpiHandle, FS_DIG0,0x50, 1); //Frequency Synthesizer Digital Reg. 0
    halRfWriteReg(&SpiHandle, FS_CAL2,0x00, 1);
    halRfWriteReg(&SpiHandle, FS_CAL1,0x40, 1); //Frequency Synthesizer Calibration Reg. 1
    halRfWriteReg(&SpiHandle, FS_CAL0,0x0E, 1); //Frequency Synthesizer Calibration Reg. 0
    halRfWriteReg(&SpiHandle, FS_DIVTWO,0x03, 1); //Frequency Synthesizer Divide by 2
    halRfWriteReg(&SpiHandle, FS_DSM0,0x33, 1); //FS Digital Synthesizer Module Configuration Reg. 0
    halRfWriteReg(&SpiHandle, FS_DVC1,0x00, 1);
    halRfWriteReg(&SpiHandle, FS_DVC0,0x17, 1); //Frequency Synthesizer Divider Chain Configuration ..
    halRfWriteReg(&SpiHandle, FS_PFD,0x00, 1); //Frequency Synthesizer Phase Frequency Detector Con..
    halRfWriteReg(&SpiHandle, FS_PRE,0x6E, 1); //Frequency Synthesizer Prescaler Configuration
    halRfWriteReg(&SpiHandle, FS_REG_DIV_CML,0x1C, 1);//Frequency Synthesizer Divider Regulator Configurat..
    halRfWriteReg(&SpiHandle, FS_SPARE,0xAC, 1); //Frequency Synthesizer Spare
    halRfWriteReg(&SpiHandle, FS_VCO0,0xB5, 1); //FS Voltage Controlled Oscillator Configuration Reg..
    halRfWriteReg(&SpiHandle, IFAMP,0x0D, 1); //Intermediate Frequency Amplifier Configuration
    halRfWriteReg(&SpiHandle, XOSC5,0x0E, 1); //Crystal Oscillator Configuration Reg. 5
    halRfWriteReg(&SpiHandle, XOSC1,0x03, 1);

  • I just looked at some of the registers, is this 38.4 kbps? If so, why are the other register settings different from the SmartRF Studio provided setting? 

  • Yes, it is 38.4 kbps. 

    The other register settings are set based on our IoT system requirement.

    Is there something wrong here? 

  • It looked like AGC_REF was a bit high.

    Would you be able to test with unmodified 38.4 kbps settings to verify that the RSSI does not saturate here?