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CC110L: CC110L SPI timing.

Part Number: CC110L

In the CC110L datasheet chapter 5.5 is written.

When CSn is pulled low, the MCU must wait until CC110L SO pin goes low before starting to transfer the
header byte. This indicates that the crystal is running. Unless the chip was in the SLEEP or XOFF states,
the SO pin will always go low immediately after taking CSn low.

Is possible to know how many time is "immediately"?

Many thanks in advance.

  • Unfortunately I do not have any exact number for this.

    Why do you need to know this? If the crystal is running it would not be a problem if you started the communication right away since the crystal is stable and everything is OK. The wait is only necessary when you come from sleep, and in this case you need to wait for SO going low.



  • Thank you very much for your prompt answare.

    we have 2 different boards with different software. The first one, after chip selection port goes down there is a 1us of delay and it works well.

    The second one do not have a delay after the chip selection port goes down, and some time the CC110L goes in stall (it remain with the carrier switched on until a new spi comunication).

    Now the new software check if the SO port go low before starting the spi comunication and it works well.
    In the first board we can't check the port condition.

    We want to know if a delay of 1us is sufficient or we take a risk if we don't check the SO port condition.

    P.S. the CC110L never is put in sleep.

    Best regards

  • Hi Fabio

    The MISO line going low (CHP_RDYn asserted) is not what makes the crystal stable, it just tells you if it is stable or not. That means that if you never go to SLEEP mode, the crystal is stable all the time (after first initial power-on) and there is no need to even check the CHP_RDYn signal.

    The only thing you should need to keep in mind is tSP (CSn low to positive edge on SCLK, in active mode). This needs to be a minimum of 20 ns.

    Please note that if you enter SLEEP state with the crystal on (XOSC_FORCE_ON = 1), you need to set PO_TIMEOUT so that the regulated digital supply voltage has time to stabilize before CHP_RDYn goes low. Again, if you are never entering SLEEP state this is not something you should need to think about as the regulated digital supply voltage will be stable all the time (after power_on).

    Can you please verify that you have a minimum of 20 ns from CSn low to positive edge on SCLK. If you have, and you still problems, please explain in details how you see the device fail.