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CC113L: AFC behavior

Sinsan
Prodigy 120 points
Part Number: CC113L
Other Parts Discussed in Thread: TEST2

Hi,

My CC113L register settings are as below.

   0x0D, // IOCFG2             GDO2 Output Pin Configuration

   0x0E, // IOCFG1             GDO1 Output Pin Configuration

   0x2E, // IOCFG0             GDO0 Output Pin Configuration

   0x47, // FIFOTHR           RX FIFO Thresholds

   0x32, // PKTCTRL0           Packet Automation Control

   0x06, // FSCTRL1           Frequency Synthesizer Control

   0x0C, // FREQ2             Frequency Control Word, High Byte

   0x10, // FREQ1             Frequency Control Word, Middle Byte

   0x00, // FREQ0             Frequency Control Word, Low Byte

   0xA8, // MDMCFG4           Modem Configuration

   0x83, // MDMCFG3           Modem Configuration

   0x00, // MDMCFG2           Modem Configuration

   0x41, // DEVIATN           Modem Deviation Setting

   0x3C, // MCSM1            Main Radio Control State Machine Configuration

   0x18, // MCSM0             Main Radio Control State Machine Configuration

   0x2E, // FOCCFG             Frequency Offset Compensation Configuration

   0x43, // AGCCTRL2           AGC Control

   0xFB, // RESERVED_0X20     Use setting from SmartRF Studio

   0xE9, // FSCAL3             Frequency Synthesizer Calibration

   0x2A, // FSCAL2             Frequency Synthesizer Calibration

   0x00, // FSCAL1             Frequency Synthesizer Calibration

   0x1F, // FSCAL0             Frequency Synthesizer Calibration

   0x81, // TEST2             Various Test Settings

   0x35, // TEST1             Various Test Settings

In case this register setting is used, does CC113L work as follows?

1. When FOCCFG.FOC_BS_CS_GATE=1 is set,

- Frequency error detector and error compensation work during the CS signal is high.

- The error detector does not work during the CS signal is low. In this period, the compensated frequency which obtained before the CS signal goes low is used.

2. When MDMCFG2.SYNC_MODE=0 (No preamble/sync) is set, AFC loop gain of FOCCFG.FOC_PRE_K will be applied during the CS signal is high.

3. When MDMCFG2.SYNC_MODE=4 (No preamble/sync, carrier-sense above threshold) is set, AFC loop gain of FOCCFG.FOC_POST_K will be applied during the CS signal is high.

Regards,

Sinsan

  • 0
    TI__Guru**** 317180 points

    Looks correct.

    What is the background for the question? 

  • 0 in reply to TER
    Prodigy 120 points

    Hi TER,

    Thank you for your response.

    I am considering to use CC113L for receiver of remote controlled equipment which is permanently in RX mode during power supply.

    The packet format used is non-standard, 1 byte preamble, no sync word and UART format.

    CC113L is configured as 2-FSK receiver. Demodulated data output is assigned to GDOx with asynchronous serial mode.

    The period to receive a signal in a day is short, and most of them are no-signal (random noise).

    In this case, I guess that to set FOCCFG.FOC_BC_CS_GATE=1 could give more reliable reception. So I asked if my understanding about the parameter usage is correct.

    Regards,

    Sinsan