• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 1 answer
  • Subscribers 54 subscribers
  • Views 242 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CC1200: CC1200 infinite mode FIFO

David Kyle
Prodigy 120 points
Part Number: CC1200

Hi

I’m having a hard time understanding the code in example swrc253e for infinite mode transmit. Specifically, in file “cc112x_infinite_packet_length_mode_tx.c” we have the #define AVAILABLE_BYTES_IN_TX_FIFO with a value of 122. The comment next to is says "# of bytes one can write to the TX_FIFO when a falling edge occur on IOCFGx = 0x02 and FIFO_THR = 120". I don’t understand this.

This implication from this comment is that “AVAILABLE_BYTES_IN_TX_FIFO” is the value programmed into FIFO_THR with an addition of “+”2” and I don’t understand where the “+2” comes from. To my mind this suggests that if we were to program FIFO_THR with a value of 127 then we could write 129 bytes to the FIFO, but this does not make sense to me because the FIFO is only 128 bytes long ?

Hopefully, someone can explain.

Thanks

David

  • 0
    TI__Guru 73541 points

    Hi David,

    I think you're misunderstanding what "+2" means in this context. These are added to make up for metadata and can not be used by you.

  • 0 in reply to Marie H
    Prodigy 120 points

    Thanks for your quick response but I’m not sure what you mean by “metadata” so please could you expand on this.

    Looking at function txFifoBelowThresholdISR() I can see the line of code:

     cc112xSpiWriteTxFifo(pBufferIndex, AVAILABLE_BYTES_IN_TX_FIFO);

    This, to me ,still implies that AVAILABLE_BYTES_IN_TX_FIFO is being used to govern how much data we write into the Fifo each time the “TXFIFO_THR” interrupt is triggered. Hence, I still do not understand. If for some reason we set FIFO_THR to 127 then AVAILABLE_BYTES_IN_TX_FIFO will be 129 which is bigger than the 128 byte FIFO ? By implication, it therefore seems wrong to set AVAILABLE_BYTES_IN_TX_FIFO to “TXFIFO_THR + 2”.

    (The description for cc112xSpiWriteTxFifo says the second parameter is the length of data to be written)

     David

  • 0 in reply to TER
    Prodigy 120 points

    Thank you again for your response. In the post you have referred me to, the original poster is asking about the “+2” addition in infinite receive mode and on the RXFIFO. Here, the total data length has +2 added to accommodate the various status fields that can be optionally appended and that are not transmitted over the air.

    I think my question is different, because I am asking about the TX FiFO. Specifically, I am asking why the example code appears to suggest that every time the FIFO is written to, and before we approach the end of the infinite mode, we send an additional two bytes to the FIFO ? I am also asking why the code suggests that if we had a FIFO_THR of 127 then the implication is that we would send 129 bytes to the 128 byte FIFO. This is the part I am struggling to understand.

    David

  • 0 in reply to David Kyle
    TI__Guru* 79421 points

    From the user guide, table 26, you will see that FIFO_THR = 120 corresponds to 7 bytes in the TX FIFO; i.e, the TX FIFO Threshold is 7 bytes.

    From the explanation of the interrupt: “De-asserted when the TX FIFO is drained below the same threshold” (the TX FIFO Threshold, which is 7)

    That means that the ISR run when the TX FIFO is drained BELOW 7 bytes, so there are now 6 bytes left in the FIFO. Since the FIFO is 128 bytes, there are now room to write 122 bytes to the FIFO.

    BR

    Siri

  • 0 in reply to Siri
    Prodigy 120 points

    Thanks Siri - that makes perfect sense. Now I understand.