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CC1310 chip erase by JTAG issue.

Terry Lung1
Prodigy 220 points

Hi,

My microcontroller has to chip erase by JTAG, because I program the pattern it will disable boot loader.

I found Doc. in page 406 have command "CHIP_ERASE_REQ". And I can read and write by 4-pin jtag to ram already, but still don't know how to into "Debug Features Supported Through WUC TAP".

I scan DR value 0x9500_0100 by following router(000010b), then scan DR(0x1500_0000) return value is 0x0003_0300. Is this value right?

Does anyone have any sample sequence or any idea to go erasing with command "CHIP_ERASE_REQ"?

And what Instruction wide is "Debug Features Supported Through WUC TAP"? All I know ICEPick is 6, and ARM is 4.

  • 0
    TI__Genius 12480 points
    Hello,

    Why do you want to perform chip erase without using standard tools? Implementing low level JTAG protocol is not straight forward...

    Suggested sequence:
    1. Enable 2-pin or 4-pin JTAG
    2. Write public connect instruction
    INFO: :13:13:52.412:Master - TX: SCAN_IR (IR write: 0x00000007, NumBits: 6)
    INFO: :13:13:52.412:Master - RX: SCAN_IR (IR read: 0x00000001)
    3. Write connect key
    INFO: :13:13:52.412:Master - TX: SCAN_DR (DR write: 0x0000000000000089, NumBits: 8)
    INFO: :13:13:52.412:Master - RX: SCAN_DR (DR read: 0x0000000000000009)
    4. Write router instruction
    INFO: :13:13:52.412:Master - TX: SCAN_IR (IR write: 0x00000002, NumBits: 6)
    INFO: :13:13:52.412:Master - RX: SCAN_IR (IR read: 0x00000001)
    5. Power up AON_WUC TAP and add to scan chain
    INFO: :13:13:52.412:Master - TX: SCAN_DR (DR write: 0x0000000095002100, NumBits: 32)
    INFO: :13:13:52.412:Master - RX: SCAN_DR (DR read: 0x0000000000000000)
    6. Write router instruction, and set AON_WUC TAP in bypass mode
    INFO: :13:33:07.111:Master - TX: SCAN_IR (IR write: 0x0000002F, NumBits: 10)
    INFO: :13:33:07.111:Master - RX: SCAN_IR (IR read: 0x00000011)
    7. Read STTR register to verify it’s 0x002303 indicating AON_WUC TAP has been added successfully.
    INFO: :13:33:07.111:Master - TX: SCAN_DR (DR write: 0x000000002A000000, NumBits: 33)
    INFO: :13:33:07.111:Master - RX: SCAN_DR (DR read: 0x000000002A004606)
    Note: (0x000000002A004606 >> 1) & 0xFFFFFF equals 0x002303
    8. Set ICEPICK in bypass mode and select AON_WUC IR = 0x01
    INFO: :13:33:07.115:Master - TX: SCAN_IR (IR write: 0x000003F1, NumBits: 10)
    INFO: :13:33:07.125:Master - RX: SCAN_IR (IR read: 0x00000011)
    9. Set bit 1 (CHIP_ERASE_REQ) and bit 5 (MCU_VD_RESET_REQ). The chip erase is done after this DR scan is performed.
    INFO: :13:33:07.125:Master - TX: SCAN_DR (DR write: 0x0000000000000022, NumBits: 9)
    INFO: :13:33:07.135:Master - RX: SCAN_DR (DR read: 0x0000000000000000)