HI, we need to control PA ramping in CC1310.
In July 2017 SVS wrote to a user:
PA ramping is configured in bits 15:8 of the value written at address 0x6088 (configured by the override). Bits 15:13 configure the PA trim time increment in steps of (8+4*2^PaTrimTime)/12 [us]. Bits 12:8 configure the the PA trim step size (zero is illegal, lower this value longer is the ramp time).
In addition, ramp time can also be setup by changing the value for bits 15:8 at address 0x608C (default is HW_REG_OVERRIDE(0x608C,0x8213)). Bits 15:13 configure the PA ramp IB time increment in steps of (8+4*2^PA ramp IB time )/12 [us]. Bits 12:8 configure the the PA ramp IB step size (zero is illegal, lower this value, longer is the ramp time).
Please refer to the following wiki for ramp settings used at higher data rates.
http://processors.wiki.ti.com/index.php/Settings_for_Different_PHY%27s
Regards,
- "PA ramping. Set HW_REG_OVERRIDE(0x6088,0x1024) and HW_REG_OVERRIDE(0x608C,0x0813). This gives a PA ramp time of approximately 5 us." I can't figure out how this number of "5 us" was derived using the explanation given by SVS.
- "Set HW_REG_OVERRIDE(0x6088,0x6119) and HW_REG_OVERRIDE(0x608C,0x8113). This gives a PA ramp time of approximately 100 us " The same - how did it result in 100 us.
Can you please explain?
Thank you,
Sergey