Question 1: whether the processing process of whitening, CRC, convolutional code, interleave and spread spectrum as shown in the figure below can be realized by hardware?
Send: rawdata-> Whitened->CRC->CC->Interleaved->Spreading->FSK is it right?Can be implemented by hardware
Receiving process: is fsk-> interleaved-> cc-> crc-> Whitened to RawData correct?Whether they all pass Hardware implementation?
Question 2: can the chip obtain the state of processing at each important stage?Like start state, end state?Can you elaborate on how to get the state, or is there any documentation?
Q3: can the chip obtain the data processed at each important stage?By what means, or is there documentation?
Question 4: what algorithms are used for albino, CRC, convolutional code, interleave and spread spectrum?What are the chapters on chip register configuration?Can you provide the algorithm keyword introduction or algorithm document introduction?
Q5: does the chip support BPSK and QPSK modulation and demodulation?
Problems with using the official development board?
1. Invalid leading code (inconsistencies in preamble between sending and receiving end can also receive data packets)
For example: sender PREAMBLE_CFG1 = 0x10, receiver PREAMBLE_CFG1 = 0x11
2. Is it possible to use only the modulating and demodulating functions of the chip to organize leading codes and synchronization codes by ourselves?
3. How should the Deviation value be determined and calculated?What are the effects of miscalculation
4. The relationship between RX Filter BW value and Symbol rate?What is the most reasonable value to set RX Filter BW?